Searched refs:BIT0 (Results 1 - 9 of 9) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/
H A Dtmscsim.h193 #define BIT0 0x00000001 macro
196 #define UNIT_ALLOCATED BIT0
202 #define DASD_SUPPORT BIT0
208 #define SRB_WAIT BIT0
225 #define SRB_OK BIT0
233 #define RESET_DEV BIT0
238 #define ABORT_DEV_ BIT0
247 #define AUTO_REQSENSE BIT0
287 #define SYNC_ENABLE BIT0
342 #define PARITY_CHK_ BIT0
[all...]
H A Ddc395x.h72 #define BIT0 0x00000001 macro
75 #define UNIT_ALLOCATED BIT0
81 #define DASD_SUPPORT BIT0
117 #define RESET_DEV BIT0
122 #define ABORT_DEV_ BIT0
125 #define SRB_OK BIT0
139 #define AUTO_REQSENSE BIT0
170 #define SYNC_NEGO_ENABLE BIT0
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-integrator/
H A Dbits.h26 #define BIT0 0x00000001 macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Dsynclink_gt.c226 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
232 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
397 #define MASK_FRAMING BIT0
437 #define IRQ_MASTER BIT0
1913 if ((status = *(p+1) & (BIT1 + BIT0))) {
1916 else if (status & BIT0)
1923 else if (status & BIT0)
3734 if (!(rd_reg32(info, RDCSR) & BIT0))
3747 if (!(rd_reg32(info, TDCSR) & BIT0))
[all...]
H A Dsynclinkmp.c430 #define RXRDYE BIT0
442 #define BRKE BIT0
443 #define IDLD BIT0
2242 while((status = read_reg(info,CST0)) & BIT0)
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2662 if (status & BIT0 << shift)
2671 if (dmastatus & BIT0 << shift)
4071 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
[all...]
H A Dsynclink.c516 #define MISC BIT0
535 #define RXSTATUS_DATA_AVAILABLE BIT0
573 #define TXSTATUS_FIFO_EMPTY BIT0
593 #define MISCSTATUS_BRG0_ZERO BIT0
619 #define SICR_BRG0_ZERO BIT0
643 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
653 #define TXSTATUS_FIFO_EMPTY BIT0
656 #define DICR_TRANSMIT BIT0
672 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
1668 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/
H A Dsynclink.h20 #define BIT0 0x0001 macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c315 #define IRQ_RXFIFO BIT0 // receive pool full
323 #define PVR_DTR BIT0
753 #define CMD_TXRESET BIT0 // transmit reset
1255 if (gis & (BIT1 + BIT0)) {
3231 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3245 val = read_reg(info, CHA + MODE) | BIT0;
3298 val |= BIT0;
3368 val |= BIT0;
3644 val |= BIT0;
3722 val |= BIT0; /*
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/
H A Dcs89x0.h467 #define BIT0 1 macro

Completed in 373 milliseconds