Lines Matching refs:BIT0
516 #define MISC BIT0
535 #define RXSTATUS_DATA_AVAILABLE BIT0
573 #define TXSTATUS_FIFO_EMPTY BIT0
593 #define MISCSTATUS_BRG0_ZERO BIT0
619 #define SICR_BRG0_ZERO BIT0
643 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
653 #define TXSTATUS_FIFO_EMPTY BIT0
656 #define DICR_TRANSMIT BIT0
672 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
1668 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
5286 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5349 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5355 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5682 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5685 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
6375 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6384 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );