Lines Matching refs:BIT0
430 #define RXRDYE BIT0
442 #define BRKE BIT0
443 #define IDLD BIT0
2242 while((status = read_reg(info,CST0)) & BIT0)
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2662 if (status & BIT0 << shift)
2671 if (dmastatus & BIT0 << shift)
4071 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4074 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4089 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4459 RegValue |= BIT0;
4472 RegValue |= (BIT1 + BIT0);
4497 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4669 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4671 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4795 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4810 RegValue &= ~BIT0;
4812 RegValue |= BIT0;