Searched refs:B0TT_3 (Results 1 - 7 of 7) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A Dmem_init.h185 #define flash_EBIU_AMBCTL0_TT B0TT_3
H A DdefBF532.h1006 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A Dmem_init.h199 #define flash_EBIU_AMBCTL0_TT B0TT_3
H A DdefBF534.h1421 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A Dmem_init.h191 #define flash_EBIU_AMBCTL0_TT B0TT_3
H A DdefBF561.h1438 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DdefBF52x_base.h1161 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ macro

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