Searched refs:PLL_DIV (Results 1 - 14 of 14) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-common/
H A Ddpmc.S294 P0.H = hi(PLL_DIV);
295 P0.L = lo(PLL_DIV);
353 P0.H = hi(PLL_DIV);
354 P0.L = lo(PLL_DIV);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S358 p0.h = hi(PLL_DIV);
359 p0.l = lo(PLL_DIV);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S404 p0.h = hi(PLL_DIV);
405 p0.l = lo(PLL_DIV);
547 p0.h = hi(PLL_DIV);
548 p0.l = lo(PLL_DIV);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S422 p0.h = hi(PLL_DIV);
423 p0.l = lo(PLL_DIV);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h54 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
55 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
H A DdefBF532.h59 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
421 /* PLL_DIV Masks */
431 /* PLL_DIV Macros */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h40 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
H A DdefBF52x_base.h43 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
625 /* PLL_DIV Masks */
632 /* PLL_DIV Macros */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h49 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
857 /* PLL_DIV Masks */
H A DcdefBF561.h54 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
55 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h46 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
47 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
H A DdefBF534.h42 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
997 /* PLL_DIV Masks */
1004 /* PLL_DIV Macros */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DcdefBF54x_base.h44 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
45 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
H A DdefBF54x_base.h42 #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ macro
2544 /* Bit masks for PLL_DIV */

Completed in 392 milliseconds