1 2/* 3 * File: include/asm-blackfin/mach-bf561/defBF561.h 4 * Based on: 5 * Author: 6 * 7 * Created: 8 * Description: 9 * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 10 * Rev: 11 * 12 * Modified: 13 * 14 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2, or (at your option) 19 * any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; see the file COPYING. 28 * If not, write to the Free Software Foundation, 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32#ifndef _DEF_BF561_H 33#define _DEF_BF561_H 34/* 35#if !defined(__ADSPBF561__) 36#warning defBF561.h should only be included for BF561 chip. 37#endif 38*/ 39/* include all Core registers and bit definitions */ 40#include <asm/mach-common/def_LPBlackfin.h> 41 42/*********************************************************************************** */ 43/* System MMR Register Map */ 44/*********************************************************************************** */ 45 46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 47 48#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 49#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 50#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 51#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 53#define CHIPID 0xFFC00014 /* Chip ID Register */ 54 55/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 56#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 57#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 58#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ 59#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ 60#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ 61#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ 62#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ 63#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ 64#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ 65#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ 66#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ 67#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ 68#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ 69#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ 70#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ 71#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ 72#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ 73#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ 74 75/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 76#define SICB_SWRST 0xFFC01100 /* reserved */ 77#define SICB_SYSCR 0xFFC01104 /* reserved */ 78#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ 79#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ 80#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ 81#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ 82#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ 83#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ 84#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ 85#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ 86#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ 87#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ 88#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ 89#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ 90#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ 91#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ 92#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ 93 94/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ 95#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ 96#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ 97#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ 98 99/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ 100#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ 101#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ 102#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ 103 104/* UART Controller (0xFFC00400 - 0xFFC004FF) */ 105#define UART_THR 0xFFC00400 /* Transmit Holding register */ 106#define UART_RBR 0xFFC00400 /* Receive Buffer register */ 107#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 108#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ 109#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 110#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ 111#define UART_LCR 0xFFC0040C /* Line Control Register */ 112#define UART_MCR 0xFFC00410 /* Modem Control Register */ 113#define UART_LSR 0xFFC00414 /* Line Status Register */ 114#define UART_MSR 0xFFC00418 /* Modem Status Register */ 115#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ 116#define UART_GCTL 0xFFC00424 /* Global Control Register */ 117 118/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 119#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 120#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 121#define SPI_STAT 0xFFC00508 /* SPI Status register */ 122#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ 123#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ 124#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ 125#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ 126 127/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ 128#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ 129#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ 130#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ 131#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ 132 133#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ 134#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ 135#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ 136#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ 137 138#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ 139#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ 140#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ 141#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ 142 143#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ 144#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ 145#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ 146#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ 147 148#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ 149#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ 150#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ 151#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ 152 153#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ 154#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ 155#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ 156#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ 157 158#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ 159#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ 160#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ 161#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ 162 163#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ 164#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ 165#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ 166#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ 167 168#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ 169#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ 170#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ 171 172/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ 173#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ 174#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ 175#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ 176#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ 177 178#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ 179#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ 180#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ 181#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ 182 183#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ 184#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ 185#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ 186#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ 187 188#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ 189#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ 190#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ 191#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ 192 193#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ 194#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ 195#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ 196 197/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ 198#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ 199#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ 200#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ 201#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ 202#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ 203#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ 204#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ 205#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ 206#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ 207#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ 208#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ 209#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ 210#define FIO0_DIR 0xFFC00730 /* Flag Direction register */ 211#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ 212#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ 213#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ 214#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ 215 216/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ 217#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */ 218#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ 219#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ 220#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */ 221#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ 222#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ 223#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ 224#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ 225#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ 226#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ 227#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ 228#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ 229#define FIO1_DIR 0xFFC01530 /* Flag Direction register */ 230#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ 231#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ 232#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ 233#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ 234 235/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ 236#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */ 237#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ 238#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ 239#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */ 240#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ 241#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ 242#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ 243#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ 244#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ 245#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ 246#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ 247#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ 248#define FIO2_DIR 0xFFC01730 /* Flag Direction register */ 249#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ 250#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ 251#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ 252#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ 253 254/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 255#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 256#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 257#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 258#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 259#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 260#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 261#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 262#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 263#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 264#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 265#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 266#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 267#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 268#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 269#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 270#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 271#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 272#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 273#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 274#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 275#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 276#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 277 278/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 279#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 280#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 281#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 282#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 283#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 284#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 285#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 286#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 287#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 288#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 289#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 290#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 291#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 292#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 293#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 294#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 295#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 296#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 297#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 298#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 299#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 300#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 301 302/* Asynchronous Memory Controller - External Bus Interface Unit */ 303#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 304#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 305#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 306 307/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 308#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 309#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 310#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 311#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 312 313/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ 314#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ 315#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ 316#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ 317#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ 318#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ 319 320/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ 321#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ 322#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ 323#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ 324#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ 325#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ 326 327/*DMA traffic control registers */ 328#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ 329#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ 330#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ 331#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ 332 333/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 334#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ 335#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ 336#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ 337#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ 338#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ 339#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ 340#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ 341#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ 342#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ 343#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ 344#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ 345#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */ 346#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ 347 348#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ 349#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ 350#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ 351#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ 352#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ 353#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ 354#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ 355#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ 356#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ 357#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ 358#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ 359#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */ 360#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ 361 362#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ 363#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ 364#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ 365#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ 366#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ 367#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ 368#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ 369#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ 370#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ 371#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ 372#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ 373#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */ 374#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ 375 376#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ 377#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ 378#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ 379#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ 380#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ 381#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ 382#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ 383#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ 384#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ 385#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ 386#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ 387#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */ 388#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ 389 390#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ 391#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ 392#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ 393#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ 394#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ 395#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ 396#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ 397#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ 398#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ 399#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ 400#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ 401#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */ 402#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ 403 404#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ 405#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ 406#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ 407#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ 408#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ 409#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ 410#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ 411#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ 412#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ 413#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ 414#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ 415#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */ 416#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ 417 418#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ 419#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ 420#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ 421#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ 422#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ 423#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ 424#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ 425#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ 426#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ 427#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ 428#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ 429#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */ 430#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ 431 432#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ 433#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ 434#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ 435#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ 436#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ 437#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ 438#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ 439#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ 440#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ 441#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ 442#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ 443#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */ 444#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ 445 446#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ 447#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ 448#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ 449#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ 450#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ 451#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ 452#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ 453#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ 454#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ 455#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ 456#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ 457#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */ 458#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ 459 460#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ 461#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ 462#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ 463#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ 464#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ 465#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ 466#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ 467#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ 468#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ 469#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ 470#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ 471#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */ 472#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ 473 474#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ 475#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ 476#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ 477#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ 478#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ 479#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ 480#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ 481#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ 482#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ 483#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ 484#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ 485#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */ 486#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ 487 488#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ 489#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ 490#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ 491#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ 492#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ 493#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ 494#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ 495#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ 496#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ 497#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ 498#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ 499#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */ 500#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ 501 502/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 503#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ 504#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ 505#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ 506#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ 507#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ 508#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ 509#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ 510#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ 511#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ 512#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ 513#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ 514#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ 515#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ 516 517#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ 518#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ 519#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ 520#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ 521#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ 522#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ 523#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ 524#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ 525#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ 526#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ 527#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ 528#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ 529#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ 530 531#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ 532#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ 533#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ 534#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ 535#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ 536#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ 537#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ 538#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ 539#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ 540#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ 541#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ 542#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ 543#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ 544 545#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ 546#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ 547#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ 548#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ 549#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ 550#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ 551#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ 552#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ 553#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ 554#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ 555#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ 556#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ 557#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ 558 559/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 560#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ 561#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ 562#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ 563#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ 564#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ 565#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ 566#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ 567#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ 568#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ 569#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ 570#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ 571#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */ 572#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ 573 574#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ 575#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ 576#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ 577#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ 578#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ 579#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ 580#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ 581#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ 582#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ 583#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ 584#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ 585#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */ 586#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ 587 588#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ 589#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ 590#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ 591#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ 592#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ 593#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ 594#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ 595#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ 596#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ 597#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ 598#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ 599#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */ 600#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ 601 602#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ 603#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ 604#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ 605#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ 606#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ 607#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ 608#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ 609#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ 610#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ 611#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ 612#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ 613#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */ 614#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ 615 616#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ 617#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ 618#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ 619#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ 620#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ 621#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ 622#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ 623#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ 624#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ 625#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ 626#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ 627#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */ 628#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ 629 630#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ 631#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ 632#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ 633#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ 634#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ 635#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ 636#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ 637#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ 638#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ 639#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ 640#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ 641#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */ 642#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ 643 644#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ 645#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ 646#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ 647#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ 648#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ 649#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ 650#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ 651#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ 652#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ 653#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ 654#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ 655#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */ 656#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ 657 658#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ 659#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ 660#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ 661#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ 662#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ 663#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ 664#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ 665#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ 666#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ 667#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ 668#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ 669#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */ 670#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ 671 672#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ 673#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ 674#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ 675#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ 676#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ 677#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ 678#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ 679#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ 680#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ 681#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ 682#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ 683#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */ 684#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ 685 686#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ 687#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ 688#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ 689#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ 690#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ 691#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ 692#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ 693#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ 694#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ 695#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ 696#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ 697#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */ 698#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ 699 700#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ 701#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ 702#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ 703#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ 704#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ 705#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ 706#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ 707#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ 708#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ 709#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ 710#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ 711#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */ 712#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ 713 714#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ 715#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ 716#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ 717#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ 718#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ 719#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ 720#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ 721#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ 722#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ 723#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ 724#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ 725#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */ 726#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ 727 728/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 729#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ 730#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ 731#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ 732#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ 733#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ 734#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ 735#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ 736#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ 737#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ 738#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ 739#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ 740#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ 741#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ 742 743#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ 744#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ 745#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ 746#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ 747#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ 748#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ 749#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ 750#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ 751#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ 752#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ 753#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ 754#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ 755#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ 756 757#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ 758#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ 759#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ 760#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ 761#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ 762#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ 763#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ 764#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ 765#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ 766#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ 767#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ 768#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ 769#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ 770 771#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ 772#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ 773#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ 774#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ 775#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ 776#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ 777#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ 778#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ 779#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ 780#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ 781#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ 782#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ 783#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ 784 785/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 786#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ 787#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ 788#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */ 789#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */ 790#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */ 791#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */ 792#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */ 793#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */ 794#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */ 795#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */ 796#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */ 797#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */ 798 799#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */ 800#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */ 801#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */ 802#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */ 803#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */ 804#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */ 805#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */ 806#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */ 807#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */ 808#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */ 809#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */ 810#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */ 811 812#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */ 813#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ 814#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */ 815#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */ 816#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */ 817#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */ 818#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */ 819#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */ 820#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */ 821#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */ 822#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */ 823#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */ 824 825#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */ 826#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */ 827#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */ 828#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */ 829#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */ 830#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */ 831#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */ 832#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */ 833#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */ 834#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */ 835#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */ 836#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */ 837 838/*********************************************************************************** */ 839/* System MMR Register Bits */ 840/******************************************************************************* */ 841 842/* ********************* PLL AND RESET MASKS ************************ */ 843 844/* PLL_CTL Masks */ 845#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ 846#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ 847#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ 848#define STOPCK_OFF 0x00000008 /* Core clock off */ 849#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ 850#define BYPASS 0x00000100 /* Bypass the PLL */ 851 852/* CHIPID Masks */ 853#define CHIPID_VERSION 0xF0000000 854#define CHIPID_FAMILY 0x0FFFF000 855#define CHIPID_MANUFACTURE 0x00000FFE 856 857/* PLL_DIV Masks */ 858#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 859 860#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ 861#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ 862#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ 863#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ 864 865/* PLL_STAT Masks */ 866#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 867#define FULL_ON 0x0002 /* Processor In Full On Mode */ 868#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 869#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 870 871/* SWRST Mask */ 872#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ 873#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ 874#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ 875#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ 876#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ 877#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ 878 879/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 880 881/* SICu_IARv Masks */ 882/* u = A or B */ 883/* v = 0 to 7 */ 884/* w = 0 or 1 */ 885 886/* Per_number = 0 to 63 */ 887/* IVG_number = 7 to 15 */ 888#define Peripheral_IVG(Per_number, IVG_number) \ 889 ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */ 890 /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */ 891 /* r0.h = hi(Peripheral_IVG(62, 10)); */ 892 893/* SICx_IMASKw Masks */ 894/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ 895#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 896#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 897#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ 898#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ 899 900/* SIC_IWR Masks */ 901#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 902#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 903/* x = pos 0 to 31, for 32-63 use value-32 */ 904#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 905#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 906 907/* ***************************** UART CONTROLLER MASKS ********************** */ 908 909/* UART_LCR Register */ 910 911#define DLAB 0x80 912#define SB 0x40 913#define STP 0x20 914#define EPS 0x10 915#define PEN 0x08 916#define STB 0x04 917#define WLS(x) ((x-5) & 0x03) 918 919#define DLAB_P 0x07 920#define SB_P 0x06 921#define STP_P 0x05 922#define EPS_P 0x04 923#define PEN_P 0x03 924#define STB_P 0x02 925#define WLS_P1 0x01 926#define WLS_P0 0x00 927 928/* UART_MCR Register */ 929#define LOOP_ENA 0x10 930#define LOOP_ENA_P 0x04 931 932/* UART_LSR Register */ 933#define TEMT 0x40 934#define THRE 0x20 935#define BI 0x10 936#define FE 0x08 937#define PE 0x04 938#define OE 0x02 939#define DR 0x01 940 941#define TEMP_P 0x06 942#define THRE_P 0x05 943#define BI_P 0x04 944#define FE_P 0x03 945#define PE_P 0x02 946#define OE_P 0x01 947#define DR_P 0x00 948 949/* UART_IER Register */ 950#define ELSI 0x04 951#define ETBEI 0x02 952#define ERBFI 0x01 953 954#define ELSI_P 0x02 955#define ETBEI_P 0x01 956#define ERBFI_P 0x00 957 958/* UART_IIR Register */ 959#define STATUS(x) ((x << 1) & 0x06) 960#define NINT 0x01 961#define STATUS_P1 0x02 962#define STATUS_P0 0x01 963#define NINT_P 0x00 964#define IIR_TX_READY 0x02 /* UART_THR empty */ 965#define IIR_RX_READY 0x04 /* Receive data ready */ 966#define IIR_LINE_CHANGE 0x06 /* Receive line status */ 967#define IIR_STATUS 0x06 968 969/* UART_GCTL Register */ 970#define FFE 0x20 971#define FPE 0x10 972#define RPOLC 0x08 973#define TPOLC 0x04 974#define IREN 0x02 975#define UCEN 0x01 976 977#define FFE_P 0x05 978#define FPE_P 0x04 979#define RPOLC_P 0x03 980#define TPOLC_P 0x02 981#define IREN_P 0x01 982#define UCEN_P 0x00 983 984/* ********** SERIAL PORT MASKS ********************** */ 985 986/* SPORTx_TCR1 Masks */ 987#define TSPEN 0x0001 /* TX enable */ 988#define ITCLK 0x0002 /* Internal TX Clock Select */ 989#define TDTYPE 0x000C /* TX Data Formatting Select */ 990#define TLSBIT 0x0010 /* TX Bit Order */ 991#define ITFS 0x0200 /* Internal TX Frame Sync Select */ 992#define TFSR 0x0400 /* TX Frame Sync Required Select */ 993#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ 994#define LTFS 0x1000 /* Low TX Frame Sync Select */ 995#define LATFS 0x2000 /* Late TX Frame Sync Select */ 996#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 997 998/* SPORTx_TCR2 Masks */ 999#define SLEN 0x001F /*TX Word Length */ 1000#define TXSE 0x0100 /*TX Secondary Enable */ 1001#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ 1002#define TRFST 0x0400 /*TX Right-First Data Order */ 1003 1004/* SPORTx_RCR1 Masks */ 1005#define RSPEN 0x0001 /* RX enable */ 1006#define IRCLK 0x0002 /* Internal RX Clock Select */ 1007#define RDTYPE 0x000C /* RX Data Formatting Select */ 1008#define RULAW 0x0008 /* u-Law enable */ 1009#define RALAW 0x000C /* A-Law enable */ 1010#define RLSBIT 0x0010 /* RX Bit Order */ 1011#define IRFS 0x0200 /* Internal RX Frame Sync Select */ 1012#define RFSR 0x0400 /* RX Frame Sync Required Select */ 1013#define LRFS 0x1000 /* Low RX Frame Sync Select */ 1014#define LARFS 0x2000 /* Late RX Frame Sync Select */ 1015#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 1016 1017/* SPORTx_RCR2 Masks */ 1018#define SLEN 0x001F /*RX Word Length */ 1019#define RXSE 0x0100 /*RX Secondary Enable */ 1020#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ 1021#define RRFST 0x0400 /*Right-First Data Order */ 1022 1023/*SPORTx_STAT Masks */ 1024#define RXNE 0x0001 /*RX FIFO Not Empty Status */ 1025#define RUVF 0x0002 /*RX Underflow Status */ 1026#define ROVF 0x0004 /*RX Overflow Status */ 1027#define TXF 0x0008 /*TX FIFO Full Status */ 1028#define TUVF 0x0010 /*TX Underflow Status */ 1029#define TOVF 0x0020 /*TX Overflow Status */ 1030#define TXHRE 0x0040 /*TX Hold Register Empty */ 1031 1032/*SPORTx_MCMC1 Masks */ 1033#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ 1034#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ 1035 1036/*SPORTx_MCMC2 Masks */ 1037#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ 1038#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ 1039#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ 1040#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ 1041#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ 1042#define MFD 0x0000F000 /*Multichannel Frame Delay */ 1043 1044/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1045 1046/* PPI_CONTROL Masks */ 1047#define PORT_EN 0x00000001 /* PPI Port Enable */ 1048#define PORT_DIR 0x00000002 /* PPI Port Direction */ 1049#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ 1050#define PORT_CFG 0x00000030 /* PPI Port Configuration */ 1051#define FLD_SEL 0x00000040 /* PPI Active Field Select */ 1052#define PACK_EN 0x00000080 /* PPI Packing Mode */ 1053#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ 1054#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ 1055#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ 1056#define DLENGTH 0x00003800 /* PPI Data Length */ 1057#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ 1058#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 1059#define POL 0x0000C000 /* PPI Signal Polarities */ 1060 1061/* PPI_STATUS Masks */ 1062#define FLD 0x00000400 /* Field Indicator */ 1063#define FT_ERR 0x00000800 /* Frame Track Error */ 1064#define OVR 0x00001000 /* FIFO Overflow Error */ 1065#define UNDR 0x00002000 /* FIFO Underrun Error */ 1066#define ERR_DET 0x00004000 /* Error Detected Indicator */ 1067#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ 1068 1069/* ********** DMA CONTROLLER MASKS *********************8 */ 1070 1071/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ 1072#define DMAEN 0x00000001 /* Channel Enable */ 1073#define WNR 0x00000002 /* Channel Direction (W/R*) */ 1074#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ 1075#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ 1076#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ 1077#define DMA2D 0x00000010 /* 2D/1D* Mode */ 1078#define RESTART 0x00000020 /* Restart */ 1079#define DI_SEL 0x00000040 /* Data Interrupt Select */ 1080#define DI_EN 0x00000080 /* Data Interrupt Enable */ 1081#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 1082#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 1083#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 1084#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 1085#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 1086#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 1087#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 1088#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 1089#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 1090#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 1091#define NDSIZE 0x00000900 /* Next Descriptor Size */ 1092#define DMAFLOW 0x00007000 /* Flow Control */ 1093#define DMAFLOW_STOP 0x0000 /* Stop Mode */ 1094#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ 1095#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 1096#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 1097#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 1098 1099#define DMAEN_P 0 /* Channel Enable */ 1100#define WNR_P 1 /* Channel Direction (W/R*) */ 1101#define DMA2D_P 4 /* 2D/1D* Mode */ 1102#define RESTART_P 5 /* Restart */ 1103#define DI_SEL_P 6 /* Data Interrupt Select */ 1104#define DI_EN_P 7 /* Data Interrupt Enable */ 1105 1106/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ 1107 1108#define DMA_DONE 0x00000001 /* DMA Done Indicator */ 1109#define DMA_ERR 0x00000002 /* DMA Error Indicator */ 1110#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ 1111#define DMA_RUN 0x00000008 /* DMA Running Indicator */ 1112 1113#define DMA_DONE_P 0 /* DMA Done Indicator */ 1114#define DMA_ERR_P 1 /* DMA Error Indicator */ 1115#define DFETCH_P 2 /* Descriptor Fetch Indicator */ 1116#define DMA_RUN_P 3 /* DMA Running Indicator */ 1117 1118/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ 1119 1120#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ 1121#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ 1122#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ 1123#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ 1124#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ 1125#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ 1126#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ 1127#define PMAP 0x00007000 /* DMA Peripheral Map Field */ 1128 1129/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 1130 1131/* PWM Timer bit definitions */ 1132 1133/* TIMER_ENABLE Register */ 1134#define TIMEN0 0x0001 1135#define TIMEN1 0x0002 1136#define TIMEN2 0x0004 1137#define TIMEN3 0x0008 1138#define TIMEN4 0x0010 1139#define TIMEN5 0x0020 1140#define TIMEN6 0x0040 1141#define TIMEN7 0x0080 1142#define TIMEN8 0x0001 1143#define TIMEN9 0x0002 1144#define TIMEN10 0x0004 1145#define TIMEN11 0x0008 1146 1147#define TIMEN0_P 0x00 1148#define TIMEN1_P 0x01 1149#define TIMEN2_P 0x02 1150#define TIMEN3_P 0x03 1151#define TIMEN4_P 0x04 1152#define TIMEN5_P 0x05 1153#define TIMEN6_P 0x06 1154#define TIMEN7_P 0x07 1155#define TIMEN8_P 0x00 1156#define TIMEN9_P 0x01 1157#define TIMEN10_P 0x02 1158#define TIMEN11_P 0x03 1159 1160/* TIMER_DISABLE Register */ 1161#define TIMDIS0 0x0001 1162#define TIMDIS1 0x0002 1163#define TIMDIS2 0x0004 1164#define TIMDIS3 0x0008 1165#define TIMDIS4 0x0010 1166#define TIMDIS5 0x0020 1167#define TIMDIS6 0x0040 1168#define TIMDIS7 0x0080 1169#define TIMDIS8 0x0001 1170#define TIMDIS9 0x0002 1171#define TIMDIS10 0x0004 1172#define TIMDIS11 0x0008 1173 1174#define TIMDIS0_P 0x00 1175#define TIMDIS1_P 0x01 1176#define TIMDIS2_P 0x02 1177#define TIMDIS3_P 0x03 1178#define TIMDIS4_P 0x04 1179#define TIMDIS5_P 0x05 1180#define TIMDIS6_P 0x06 1181#define TIMDIS7_P 0x07 1182#define TIMDIS8_P 0x00 1183#define TIMDIS9_P 0x01 1184#define TIMDIS10_P 0x02 1185#define TIMDIS11_P 0x03 1186 1187/* TIMER_STATUS Register */ 1188#define TIMIL0 0x00000001 1189#define TIMIL1 0x00000002 1190#define TIMIL2 0x00000004 1191#define TIMIL3 0x00000008 1192#define TIMIL4 0x00010000 1193#define TIMIL5 0x00020000 1194#define TIMIL6 0x00040000 1195#define TIMIL7 0x00080000 1196#define TIMIL8 0x0001 1197#define TIMIL9 0x0002 1198#define TIMIL10 0x0004 1199#define TIMIL11 0x0008 1200#define TOVF_ERR0 0x00000010 1201#define TOVF_ERR1 0x00000020 1202#define TOVF_ERR2 0x00000040 1203#define TOVF_ERR3 0x00000080 1204#define TOVF_ERR4 0x00100000 1205#define TOVF_ERR5 0x00200000 1206#define TOVF_ERR6 0x00400000 1207#define TOVF_ERR7 0x00800000 1208#define TOVF_ERR8 0x0010 1209#define TOVF_ERR9 0x0020 1210#define TOVF_ERR10 0x0040 1211#define TOVF_ERR11 0x0080 1212#define TRUN0 0x00001000 1213#define TRUN1 0x00002000 1214#define TRUN2 0x00004000 1215#define TRUN3 0x00008000 1216#define TRUN4 0x10000000 1217#define TRUN5 0x20000000 1218#define TRUN6 0x40000000 1219#define TRUN7 0x80000000 1220#define TRUN8 0x1000 1221#define TRUN9 0x2000 1222#define TRUN10 0x4000 1223#define TRUN11 0x8000 1224 1225#define TIMIL0_P 0x00 1226#define TIMIL1_P 0x01 1227#define TIMIL2_P 0x02 1228#define TIMIL3_P 0x03 1229#define TIMIL4_P 0x10 1230#define TIMIL5_P 0x11 1231#define TIMIL6_P 0x12 1232#define TIMIL7_P 0x13 1233#define TIMIL8_P 0x00 1234#define TIMIL9_P 0x01 1235#define TIMIL10_P 0x02 1236#define TIMIL11_P 0x03 1237#define TOVF_ERR0_P 0x04 1238#define TOVF_ERR1_P 0x05 1239#define TOVF_ERR2_P 0x06 1240#define TOVF_ERR3_P 0x07 1241#define TOVF_ERR4_P 0x14 1242#define TOVF_ERR5_P 0x15 1243#define TOVF_ERR6_P 0x16 1244#define TOVF_ERR7_P 0x17 1245#define TOVF_ERR8_P 0x04 1246#define TOVF_ERR9_P 0x05 1247#define TOVF_ERR10_P 0x06 1248#define TOVF_ERR11_P 0x07 1249#define TRUN0_P 0x0C 1250#define TRUN1_P 0x0D 1251#define TRUN2_P 0x0E 1252#define TRUN3_P 0x0F 1253#define TRUN4_P 0x1C 1254#define TRUN5_P 0x1D 1255#define TRUN6_P 0x1E 1256#define TRUN7_P 0x1F 1257#define TRUN8_P 0x0C 1258#define TRUN9_P 0x0D 1259#define TRUN10_P 0x0E 1260#define TRUN11_P 0x0F 1261 1262/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 1263#define TOVL_ERR0 TOVF_ERR0 1264#define TOVL_ERR1 TOVF_ERR1 1265#define TOVL_ERR2 TOVF_ERR2 1266#define TOVL_ERR3 TOVF_ERR3 1267#define TOVL_ERR4 TOVF_ERR4 1268#define TOVL_ERR5 TOVF_ERR5 1269#define TOVL_ERR6 TOVF_ERR6 1270#define TOVL_ERR7 TOVF_ERR7 1271#define TOVL_ERR8 TOVF_ERR8 1272#define TOVL_ERR9 TOVF_ERR9 1273#define TOVL_ERR10 TOVF_ERR10 1274#define TOVL_ERR11 TOVF_ERR11 1275#define TOVL_ERR0_P TOVF_ERR0_P 1276#define TOVL_ERR1_P TOVF_ERR1_P 1277#define TOVL_ERR2_P TOVF_ERR2_P 1278#define TOVL_ERR3_P TOVF_ERR3_P 1279#define TOVL_ERR4_P TOVF_ERR4_P 1280#define TOVL_ERR5_P TOVF_ERR5_P 1281#define TOVL_ERR6_P TOVF_ERR6_P 1282#define TOVL_ERR7_P TOVF_ERR7_P 1283#define TOVL_ERR8_P TOVF_ERR8_P 1284#define TOVL_ERR9_P TOVF_ERR9_P 1285#define TOVL_ERR10_P TOVF_ERR10_P 1286#define TOVL_ERR11_P TOVF_ERR11_P 1287 1288/* TIMERx_CONFIG Registers */ 1289#define PWM_OUT 0x0001 1290#define WDTH_CAP 0x0002 1291#define EXT_CLK 0x0003 1292#define PULSE_HI 0x0004 1293#define PERIOD_CNT 0x0008 1294#define IRQ_ENA 0x0010 1295#define TIN_SEL 0x0020 1296#define OUT_DIS 0x0040 1297#define CLK_SEL 0x0080 1298#define TOGGLE_HI 0x0100 1299#define EMU_RUN 0x0200 1300#define ERR_TYP(x) ((x & 0x03) << 14) 1301 1302#define TMODE_P0 0x00 1303#define TMODE_P1 0x01 1304#define PULSE_HI_P 0x02 1305#define PERIOD_CNT_P 0x03 1306#define IRQ_ENA_P 0x04 1307#define TIN_SEL_P 0x05 1308#define OUT_DIS_P 0x06 1309#define CLK_SEL_P 0x07 1310#define TOGGLE_HI_P 0x08 1311#define EMU_RUN_P 0x09 1312#define ERR_TYP_P0 0x0E 1313#define ERR_TYP_P1 0x0F 1314 1315/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ 1316 1317/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ 1318#define PF0 0x0001 1319#define PF1 0x0002 1320#define PF2 0x0004 1321#define PF3 0x0008 1322#define PF4 0x0010 1323#define PF5 0x0020 1324#define PF6 0x0040 1325#define PF7 0x0080 1326#define PF8 0x0100 1327#define PF9 0x0200 1328#define PF10 0x0400 1329#define PF11 0x0800 1330#define PF12 0x1000 1331#define PF13 0x2000 1332#define PF14 0x4000 1333#define PF15 0x8000 1334 1335/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ 1336#define PF0_P 0 1337#define PF1_P 1 1338#define PF2_P 2 1339#define PF3_P 3 1340#define PF4_P 4 1341#define PF5_P 5 1342#define PF6_P 6 1343#define PF7_P 7 1344#define PF8_P 8 1345#define PF9_P 9 1346#define PF10_P 10 1347#define PF11_P 11 1348#define PF12_P 12 1349#define PF13_P 13 1350#define PF14_P 14 1351#define PF15_P 15 1352 1353/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ 1354 1355/* SPI_CTL Masks */ 1356#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ 1357#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ 1358#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ 1359#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ 1360#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ 1361#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ 1362#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ 1363#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ 1364#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ 1365#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ 1366#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ 1367#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ 1368 1369/* SPI_FLG Masks */ 1370#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ 1371#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ 1372#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ 1373#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ 1374#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ 1375#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ 1376#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ 1377#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ 1378#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ 1379#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 1380#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 1381#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 1382#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 1383#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ 1384 1385/* SPI_FLG Bit Positions */ 1386#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ 1387#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ 1388#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ 1389#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ 1390#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ 1391#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ 1392#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ 1393#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ 1394#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ 1395#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 1396#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 1397#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 1398#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 1399#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ 1400 1401/* SPI_STAT Masks */ 1402#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ 1403#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ 1404#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ 1405#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ 1406#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ 1407#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ 1408#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ 1409 1410/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1411 1412/* AMGCTL Masks */ 1413#define AMCKEN 0x0001 /* Enable CLKOUT */ 1414#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ 1415#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 1416#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 1417#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ 1418#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ 1419#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ 1420#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ 1421#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ 1422 1423/* AMGCTL Bit Positions */ 1424#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ 1425#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ 1426#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ 1427#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ 1428#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ 1429#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ 1430#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ 1431#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ 1432 1433/* AMBCTL0 Masks */ 1434#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ 1435#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ 1436#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ 1437#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ 1438#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ 1439#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ 1440#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ 1441#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ 1442#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ 1443#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ 1444#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ 1445#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ 1446#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ 1447#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ 1448#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ 1449#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ 1450#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ 1451#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ 1452#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ 1453#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ 1454#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ 1455#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ 1456#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ 1457#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ 1458#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ 1459#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ 1460#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ 1461#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ 1462#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ 1463#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ 1464#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ 1465#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ 1466#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ 1467#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ 1468#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ 1469#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ 1470#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ 1471#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ 1472#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ 1473#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ 1474#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ 1475#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ 1476#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ 1477#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ 1478#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ 1479#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ 1480#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ 1481#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ 1482#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ 1483#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ 1484#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1485#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1486#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1487#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1488#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1489#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1490#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1491#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1492#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ 1493#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ 1494#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ 1495#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ 1496#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ 1497#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ 1498#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ 1499#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ 1500#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ 1501#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ 1502#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ 1503#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ 1504#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ 1505#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ 1506#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ 1507#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ 1508#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ 1509#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ 1510#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ 1511#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ 1512#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ 1513#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ 1514#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ 1515#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ 1516#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ 1517#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ 1518#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ 1519#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ 1520#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ 1521#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ 1522 1523/* AMBCTL1 Masks */ 1524#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ 1525#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ 1526#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ 1527#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ 1528#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ 1529#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ 1530#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1531#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1532#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1533#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1534#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1535#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1536#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1537#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1538#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ 1539#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ 1540#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ 1541#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ 1542#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ 1543#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ 1544#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ 1545#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ 1546#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ 1547#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ 1548#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ 1549#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ 1550#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ 1551#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ 1552#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ 1553#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ 1554#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ 1555#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ 1556#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ 1557#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ 1558#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ 1559#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ 1560#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ 1561#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ 1562#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ 1563#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ 1564#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ 1565#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ 1566#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ 1567#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ 1568#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ 1569#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ 1570#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ 1571#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ 1572#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ 1573#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ 1574#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1575#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1576#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1577#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1578#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1579#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1580#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1581#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1582#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ 1583#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ 1584#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ 1585#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ 1586#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ 1587#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ 1588#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ 1589#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ 1590#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ 1591#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ 1592#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ 1593#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ 1594#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ 1595#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ 1596#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ 1597#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ 1598#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ 1599#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ 1600#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ 1601#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ 1602#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ 1603#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ 1604#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ 1605#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ 1606#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ 1607#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ 1608#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ 1609#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ 1610#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ 1611#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ 1612 1613/* ********************** SDRAM CONTROLLER MASKS *************************** */ 1614 1615/* EBIU_SDGCTL Masks */ 1616#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ 1617#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ 1618#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 1619#define PFE 0x00000010 /* Enable SDRAM prefetch */ 1620#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 1621#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 1622#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 1623#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 1624#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ 1625#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ 1626#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ 1627#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ 1628#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ 1629#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ 1630#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ 1631#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ 1632#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ 1633#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ 1634#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ 1635#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ 1636#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ 1637#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ 1638#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ 1639#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ 1640#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ 1641#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ 1642#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ 1643#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ 1644#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ 1645#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ 1646#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ 1647#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ 1648#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ 1649#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ 1650#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ 1651#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ 1652#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ 1653#define PUPSD 0x00200000 /*Power-up start delay */ 1654#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ 1655#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ 1656#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ 1657#define EBUFE 0x02000000 /* Enable external buffering timing */ 1658#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ 1659#define EMREN 0x10000000 /* Extended mode register enable */ 1660#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ 1661#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ 1662 1663/* EBIU_SDBCTL Masks */ 1664#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */ 1665#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 1666#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ 1667#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ 1668#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ 1669#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 1670#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ 1671#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ 1672#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ 1673 1674#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */ 1675#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 1676#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */ 1677#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */ 1678#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */ 1679#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 1680#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */ 1681#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */ 1682#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */ 1683 1684#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */ 1685#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 1686#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */ 1687#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */ 1688#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */ 1689#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 1690#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */ 1691#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */ 1692#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */ 1693 1694#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */ 1695#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 1696#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */ 1697#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */ 1698#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */ 1699#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 1700#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */ 1701#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */ 1702#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */ 1703 1704/* EBIU_SDSTAT Masks */ 1705#define SDCI 0x00000001 /* SDRAM controller is idle */ 1706#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ 1707#define SDPUA 0x00000004 /* SDRAM power up active */ 1708#define SDRS 0x00000008 /* SDRAM is in reset state */ 1709#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1710#define BGSTAT 0x00000020 /* Bus granted */ 1711 1712#endif /* _DEF_BF561_H */ 1713