Searched refs:EBIU_AMGCTL (Results 1 - 13 of 13) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S186 p2.h = hi(EBIU_AMGCTL);
187 p2.l = lo(EBIU_AMGCTL);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S240 p2.h = hi(EBIU_AMGCTL);
241 p2.l = lo(EBIU_AMGCTL);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S231 p2.h = hi(EBIU_AMGCTL);
232 p2.l = lo(EBIU_AMGCTL);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h494 #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
495 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
H A DdefBF532.h202 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h403 #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
404 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
H A DdefBF52x_base.h231 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ macro
1148 /* EBIU_AMGCTL Masks */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h303 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ macro
H A DcdefBF561.h536 #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
537 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h386 #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
387 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
H A DdefBF534.h210 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ macro
1408 /* EBIU_AMGCTL Masks */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DcdefBF54x_base.h266 #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
267 #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
H A DdefBF54x_base.h170 #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ macro
1761 /* Bit masks for EBIU_AMGCTL */

Completed in 425 milliseconds