Searched refs:EBIU_AMBCTL0 (Results 1 - 13 of 13) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S179 p2.h = hi(EBIU_AMBCTL0);
180 p2.l = lo(EBIU_AMBCTL0);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S233 p2.h = hi(EBIU_AMBCTL0);
234 p2.l = lo(EBIU_AMBCTL0);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S224 p2.h = hi(EBIU_AMBCTL0);
225 p2.l = lo(EBIU_AMBCTL0);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h496 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
497 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
H A DdefBF532.h203 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h405 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
406 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
H A DdefBF52x_base.h232 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
1156 /* EBIU_AMBCTL0 Masks */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h304 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
H A DcdefBF561.h538 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
539 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h388 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
389 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
H A DdefBF534.h211 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
1416 /* EBIU_AMBCTL0 Masks */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DdefBF54x_base.h171 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ macro
1767 /* Bit masks for EBIU_AMBCTL0 */
4891 #define EBIU_AMCBCTL0 EBIU_AMBCTL0
H A DcdefBF54x_base.h268 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
269 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)

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