Searched refs:CPLB_L1_CHBL (Results 1 - 5 of 5) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/
H A Dcplb.h39 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
40 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
49 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A Dbf533.h256 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
265 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
268 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A Dbf537.h236 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
245 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
248 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A Dbf561.h332 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
341 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
344 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-common/
H A Ddef_LPBlackfin.h656 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable macro

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