1/* 2 * File: include/asm-blackfin/mach-bf533/bf533.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 8 * 9 * Modified: 10 * Copyright 2004-2006 Analog Devices Inc. 11 * 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, see the file COPYING, or write 26 * to the Free Software Foundation, Inc., 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 28 */ 29 30#ifndef __MACH_BF533_H__ 31#define __MACH_BF533_H__ 32 33#define SUPPORTED_REVID 2 34 35#define OFFSET_(x) ((x) & 0x0000FFFF) 36 37/*some misc defines*/ 38#define IMASK_IVG15 0x8000 39#define IMASK_IVG14 0x4000 40#define IMASK_IVG13 0x2000 41#define IMASK_IVG12 0x1000 42 43#define IMASK_IVG11 0x0800 44#define IMASK_IVG10 0x0400 45#define IMASK_IVG9 0x0200 46#define IMASK_IVG8 0x0100 47 48#define IMASK_IVG7 0x0080 49#define IMASK_IVGTMR 0x0040 50#define IMASK_IVGHW 0x0020 51 52/***************************/ 53 54 55#define BLKFIN_DSUBBANKS 4 56#define BLKFIN_DWAYS 2 57#define BLKFIN_DLINES 64 58#define BLKFIN_ISUBBANKS 4 59#define BLKFIN_IWAYS 4 60#define BLKFIN_ILINES 32 61 62#define WAY0_L 0x1 63#define WAY1_L 0x2 64#define WAY01_L 0x3 65#define WAY2_L 0x4 66#define WAY02_L 0x5 67#define WAY12_L 0x6 68#define WAY012_L 0x7 69 70#define WAY3_L 0x8 71#define WAY03_L 0x9 72#define WAY13_L 0xA 73#define WAY013_L 0xB 74 75#define WAY32_L 0xC 76#define WAY320_L 0xD 77#define WAY321_L 0xE 78#define WAYALL_L 0xF 79 80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ 81 82/* IAR0 BIT FIELDS*/ 83#define RTC_ERROR_BIT 0x0FFFFFFF 84#define UART_ERROR_BIT 0xF0FFFFFF 85#define SPORT1_ERROR_BIT 0xFF0FFFFF 86#define SPI_ERROR_BIT 0xFFF0FFFF 87#define SPORT0_ERROR_BIT 0xFFFF0FFF 88#define PPI_ERROR_BIT 0xFFFFF0FF 89#define DMA_ERROR_BIT 0xFFFFFF0F 90#define PLLWAKE_ERROR_BIT 0xFFFFFFFF 91 92/* IAR1 BIT FIELDS*/ 93#define DMA7_UARTTX_BIT 0x0FFFFFFF 94#define DMA6_UARTRX_BIT 0xF0FFFFFF 95#define DMA5_SPI_BIT 0xFF0FFFFF 96#define DMA4_SPORT1TX_BIT 0xFFF0FFFF 97#define DMA3_SPORT1RX_BIT 0xFFFF0FFF 98#define DMA2_SPORT0TX_BIT 0xFFFFF0FF 99#define DMA1_SPORT0RX_BIT 0xFFFFFF0F 100#define DMA0_PPI_BIT 0xFFFFFFFF 101 102/* IAR2 BIT FIELDS*/ 103#define WDTIMER_BIT 0x0FFFFFFF 104#define MEMDMA1_BIT 0xF0FFFFFF 105#define MEMDMA0_BIT 0xFF0FFFFF 106#define PFB_BIT 0xFFF0FFFF 107#define PFA_BIT 0xFFFF0FFF 108#define TIMER2_BIT 0xFFFFF0FF 109#define TIMER1_BIT 0xFFFFFF0F 110#define TIMER0_BIT 0xFFFFFFFF 111 112/********************************* EBIU Settings ************************************/ 113#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) 114#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) 115 116#ifdef CONFIG_C_AMBEN_ALL 117#define V_AMBEN AMBEN_ALL 118#endif 119#ifdef CONFIG_C_AMBEN 120#define V_AMBEN 0x0 121#endif 122#ifdef CONFIG_C_AMBEN_B0 123#define V_AMBEN AMBEN_B0 124#endif 125#ifdef CONFIG_C_AMBEN_B0_B1 126#define V_AMBEN AMBEN_B0_B1 127#endif 128#ifdef CONFIG_C_AMBEN_B0_B1_B2 129#define V_AMBEN AMBEN_B0_B1_B2 130#endif 131#ifdef CONFIG_C_AMCKEN 132#define V_AMCKEN AMCKEN 133#else 134#define V_AMCKEN 0x0 135#endif 136#ifdef CONFIG_C_CDPRIO 137#define V_CDPRIO 0x100 138#else 139#define V_CDPRIO 0x0 140#endif 141 142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 143 144#define MAX_VC 650000000 145#define MIN_VC 50000000 146 147#ifdef CONFIG_BFIN_KERNEL_CLOCK 148/********************************PLL Settings **************************************/ 149#if (CONFIG_VCO_MULT < 0) 150#error "VCO Multiplier is less than 0. Please select a different value" 151#endif 152 153#if (CONFIG_VCO_MULT == 0) 154#error "VCO Multiplier should be greater than 0. Please select a different value" 155#endif 156 157#if (CONFIG_VCO_MULT > 64) 158#error "VCO Multiplier is more than 64. Please select a different value" 159#endif 160 161#ifndef CONFIG_CLKIN_HALF 162#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) 163#else 164#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) 165#endif 166 167#ifndef CONFIG_PLL_BYPASS 168#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) 169#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) 170#else 171#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ 172#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ 173#endif 174 175#if (CONFIG_SCLK_DIV < 1) 176#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" 177#endif 178 179#if (CONFIG_SCLK_DIV > 15) 180#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" 181#endif 182 183#if (CONFIG_CCLK_DIV != 1) 184#if (CONFIG_CCLK_DIV != 2) 185#if (CONFIG_CCLK_DIV != 4) 186#if (CONFIG_CCLK_DIV != 8) 187#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" 188#endif 189#endif 190#endif 191#endif 192 193#if (CONFIG_VCO_HZ > MAX_VC) 194#error "VCO selected is more than maximum value. Please change the VCO multipler" 195#endif 196 197#if (CONFIG_SCLK_HZ > 133000000) 198#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" 199#endif 200 201#if (CONFIG_SCLK_HZ < 27000000) 202#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" 203#endif 204 205#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) 206#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) 207#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) 208#error "Please select sclk less than cclk" 209#endif 210#endif 211#endif 212 213#if (CONFIG_CCLK_DIV == 1) 214#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 215#endif 216#if (CONFIG_CCLK_DIV == 2) 217#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 218#endif 219#if (CONFIG_CCLK_DIV == 4) 220#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 221#endif 222#if (CONFIG_CCLK_DIV == 8) 223#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 224#endif 225#ifndef CONFIG_CCLK_ACT_DIV 226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly 227#endif 228 229#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) 230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK 231#endif 232 233#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 234 235#ifdef CONFIG_BF533 236#define CPU "BF533" 237#define CPUID 0x027a5000 238#endif 239#ifdef CONFIG_BF532 240#define CPU "BF532" 241#define CPUID 0x0275A000 242#endif 243#ifdef CONFIG_BF531 244#define CPU "BF531" 245#define CPUID 0x027a5000 246#endif 247#ifndef CPU 248#define CPU "UNKNOWN" 249#define CPUID 0x0 250#endif 251 252#if (CONFIG_MEM_SIZE % 4) 253#error "SDRAM mem size must be multible of 4MB" 254#endif 255 256#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) 257#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) 258#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) 259#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) 260 261/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ 262 263#define ANOMALY_05000158_WORKAROUND 0x200 264#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ 265#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ 266 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 267#else /*Write Through */ 268#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \ 269 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 270#endif 271 272#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) 273#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) 274#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) 275#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) 276 277#define SIZE_1K 0x00000400 /* 1K */ 278#define SIZE_4K 0x00001000 /* 4K */ 279#define SIZE_1M 0x00100000 /* 1M */ 280#define SIZE_4M 0x00400000 /* 4M */ 281 282#define MAX_CPLBS (16 * 2) 283 284/* 285* Number of required data CPLB switchtable entries 286* MEMSIZE / 4 (we mostly install 4M page size CPLBs 287* approx 16 for smaller 1MB page size CPLBs for allignment purposes 288* 1 for L1 Data Memory 289* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 290* 1 for ASYNC Memory 291*/ 292 293 294#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) 295 296/* 297* Number of required instruction CPLB switchtable entries 298* MEMSIZE / 4 (we mostly install 4M page size CPLBs 299* approx 12 for smaller 1MB page size CPLBs for allignment purposes 300* 1 for L1 Instruction Memory 301* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 302*/ 303 304#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) 305 306#endif /* __MACH_BF533_H__ */ 307