1/* 2 * File: include/asm-blackfin/mach-bf537/bf537.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537 8 * 9 * Modified: 10 * Copyright 2004-2006 Analog Devices Inc. 11 * 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, see the file COPYING, or write 26 * to the Free Software Foundation, Inc., 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 28 */ 29 30#ifndef __MACH_BF537_H__ 31#define __MACH_BF537_H__ 32 33#define SUPPORTED_REVID 2 34 35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ 36 37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ 38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ 39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ 40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ 41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ 42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ 43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ 44 45#define OFFSET_(x) ((x) & 0x0000FFFF) 46 47/*some misc defines*/ 48#define IMASK_IVG15 0x8000 49#define IMASK_IVG14 0x4000 50#define IMASK_IVG13 0x2000 51#define IMASK_IVG12 0x1000 52 53#define IMASK_IVG11 0x0800 54#define IMASK_IVG10 0x0400 55#define IMASK_IVG9 0x0200 56#define IMASK_IVG8 0x0100 57 58#define IMASK_IVG7 0x0080 59#define IMASK_IVGTMR 0x0040 60#define IMASK_IVGHW 0x0020 61 62/***************************/ 63 64 65#define BLKFIN_DSUBBANKS 4 66#define BLKFIN_DWAYS 2 67#define BLKFIN_DLINES 64 68#define BLKFIN_ISUBBANKS 4 69#define BLKFIN_IWAYS 4 70#define BLKFIN_ILINES 32 71 72#define WAY0_L 0x1 73#define WAY1_L 0x2 74#define WAY01_L 0x3 75#define WAY2_L 0x4 76#define WAY02_L 0x5 77#define WAY12_L 0x6 78#define WAY012_L 0x7 79 80#define WAY3_L 0x8 81#define WAY03_L 0x9 82#define WAY13_L 0xA 83#define WAY013_L 0xB 84 85#define WAY32_L 0xC 86#define WAY320_L 0xD 87#define WAY321_L 0xE 88#define WAYALL_L 0xF 89 90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ 91 92/********************************* EBIU Settings ************************************/ 93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) 94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) 95 96#ifdef CONFIG_C_AMBEN_ALL 97#define V_AMBEN AMBEN_ALL 98#endif 99#ifdef CONFIG_C_AMBEN 100#define V_AMBEN 0x0 101#endif 102#ifdef CONFIG_C_AMBEN_B0 103#define V_AMBEN AMBEN_B0 104#endif 105#ifdef CONFIG_C_AMBEN_B0_B1 106#define V_AMBEN AMBEN_B0_B1 107#endif 108#ifdef CONFIG_C_AMBEN_B0_B1_B2 109#define V_AMBEN AMBEN_B0_B1_B2 110#endif 111#ifdef CONFIG_C_AMCKEN 112#define V_AMCKEN AMCKEN 113#else 114#define V_AMCKEN 0x0 115#endif 116#ifdef CONFIG_C_CDPRIO 117#define V_CDPRIO 0x100 118#else 119#define V_CDPRIO 0x0 120#endif 121 122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 123 124#define MAX_VC 650000000 125#define MIN_VC 50000000 126 127/********************************PLL Settings **************************************/ 128#ifdef CONFIG_BFIN_KERNEL_CLOCK 129#if (CONFIG_VCO_MULT < 0) 130#error "VCO Multiplier is less than 0. Please select a different value" 131#endif 132 133#if (CONFIG_VCO_MULT == 0) 134#error "VCO Multiplier should be greater than 0. Please select a different value" 135#endif 136 137#if (CONFIG_VCO_MULT > 64) 138#error "VCO Multiplier is more than 64. Please select a different value" 139#endif 140 141#ifndef CONFIG_CLKIN_HALF 142#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) 143#else 144#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) 145#endif 146 147#ifndef CONFIG_PLL_BYPASS 148#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) 149#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) 150#else 151#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ 152#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ 153#endif 154 155#if (CONFIG_SCLK_DIV < 1) 156#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" 157#endif 158 159#if (CONFIG_SCLK_DIV > 15) 160#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" 161#endif 162 163#if (CONFIG_CCLK_DIV != 1) 164#if (CONFIG_CCLK_DIV != 2) 165#if (CONFIG_CCLK_DIV != 4) 166#if (CONFIG_CCLK_DIV != 8) 167#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" 168#endif 169#endif 170#endif 171#endif 172 173#if (CONFIG_VCO_HZ > MAX_VC) 174#error "VCO selected is more than maximum value. Please change the VCO multipler" 175#endif 176 177#if (CONFIG_SCLK_HZ > 133000000) 178#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" 179#endif 180 181#if (CONFIG_SCLK_HZ < 27000000) 182#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" 183#endif 184 185#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) 186#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) 187#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) 188#error "Please select sclk less than cclk" 189#endif 190#endif 191#endif 192 193#if (CONFIG_CCLK_DIV == 1) 194#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 195#endif 196#if (CONFIG_CCLK_DIV == 2) 197#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 198#endif 199#if (CONFIG_CCLK_DIV == 4) 200#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 201#endif 202#if (CONFIG_CCLK_DIV == 8) 203#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 204#endif 205#ifndef CONFIG_CCLK_ACT_DIV 206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly 207#endif 208 209#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) 210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK 211#endif 212 213#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 214 215#ifdef CONFIG_BF537 216#define CPU "BF537" 217#define CPUID 0x027c8000 218#endif 219#ifdef CONFIG_BF536 220#define CPU "BF536" 221#define CPUID 0x027c8000 222#endif 223#ifdef CONFIG_BF534 224#define CPU "BF534" 225#define CPUID 0x027c6000 226#endif 227#ifndef CPU 228#define CPU "UNKNOWN" 229#define CPUID 0x0 230#endif 231 232#if (CONFIG_MEM_SIZE % 4) 233#error "SDRAM mem size must be multible of 4MB" 234#endif 235 236#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) 237#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) 238#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) 239#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) 240 241/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ 242 243#define ANOMALY_05000158_WORKAROUND 0x200 244#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ 245#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ 246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 247#else /*Write Through */ 248#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ 249 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) 250#endif 251 252 253#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) 254#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) 255#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) 256#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) 257 258#define SIZE_1K 0x00000400 /* 1K */ 259#define SIZE_4K 0x00001000 /* 4K */ 260#define SIZE_1M 0x00100000 /* 1M */ 261#define SIZE_4M 0x00400000 /* 4M */ 262 263#define MAX_CPLBS (16 * 2) 264 265/* 266* Number of required data CPLB switchtable entries 267* MEMSIZE / 4 (we mostly install 4M page size CPLBs 268* approx 16 for smaller 1MB page size CPLBs for allignment purposes 269* 1 for L1 Data Memory 270* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 271* 1 for ASYNC Memory 272*/ 273 274 275#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) 276 277/* 278* Number of required instruction CPLB switchtable entries 279* MEMSIZE / 4 (we mostly install 4M page size CPLBs 280* approx 12 for smaller 1MB page size CPLBs for allignment purposes 281* 1 for L1 Instruction Memory 282* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 283*/ 284 285#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) 286 287#endif /* __MACH_BF537_H__ */ 288