Searched refs:BIT7 (Results 1 - 8 of 8) sorted by relevance
| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-integrator/ |
| H A D | bits.h | 33 #define BIT7 0x00000080 macro
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/scsi/ |
| H A D | tmscsim.h | 186 #define BIT7 0x00000080 macro
215 #define SRB_DISCONNECT BIT7
241 #define DATAOUT BIT7
372 #define DMA_COMMAND BIT7
398 #define INTERRUPT BIT7
407 #define SCSI_RESET BIT7
431 #define EXTENDED_TIMING BIT7
441 #define ID_MSG_CHECK BIT7
449 #define EATER_25NS BIT7
451 #define EATER_0NS (BIT7
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| H A D | dc395x.h | 65 #define BIT7 0x00000080 macro
133 #define DATAOUT BIT7
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/linux/ |
| H A D | synclink.h | 27 #define BIT7 0x0080 macro
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 310 #define IRQ_RXEOM BIT7 // receive message end
747 #define CMD_RXFIFO BIT7 // release current rx FIFO
993 // BIT7:parity error
996 if (status & (BIT7 + BIT6)) {
997 if (status & BIT7)
1008 if (status & BIT7)
1305 if (gis & BIT7) {
1552 info->read_status_mask |= BIT7 | BIT6;
1554 info->ignore_status_mask |= BIT7 | BIT6;
3397 val |= BIT7
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/ |
| H A D | synclink_gt.c | 432 #define IRQ_DSR BIT7
2825 val |= BIT7;
2827 val &= ~BIT7;
3997 val |= BIT7;
4130 val |= BIT7;
4238 val |= BIT7; /* 100, txclk = DPLL Input */
4261 val = BIT7; break;
4264 val = BIT7 + BIT6; break;
4388 val |= BIT7 + BIT6 + BIT5; /* 1110 */
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| H A D | synclink.c | 525 #define RXSTATUS_EXITED_HUNT BIT7
565 #define TXSTATUS_PREAMBLE_SENT BIT7
586 #define MISCSTATUS_DCD_LATCHED BIT7
610 #define SICR_DCD_ACTIVE BIT7
612 #define SICR_DCD (BIT7+BIT6)
646 #define TXSTATUS_PREAMBLE_SENT BIT7
2934 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2936 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
5257 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5296 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7
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| H A D | synclinkmp.c | 427 #define TXINTE BIT7
433 #define UDRN BIT7
446 #define EOM BIT7
2422 /* BIT7 = EOT (end of transfer)
2683 if (timerstatus0 & (BIT7 | BIT6))
2687 if (timerstatus1 & (BIT7 | BIT6))
4617 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4618 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4619 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
5196 /* DMA Master Enable, BIT7
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