Searched refs:BIT12 (Results 1 - 7 of 7) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-integrator/
H A Dbits.h38 #define BIT12 0x00001000 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/scsi/
H A Dtmscsim.h181 #define BIT12 0x00001000 macro
220 #define SRB_ABORT_SENT BIT12
H A Ddc395x.h60 #define BIT12 0x00001000 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/linux/
H A Dsynclink.h32 #define BIT12 0x1000 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/
H A Dsynclink.c581 #define MISCSTATUS_TXC BIT12
602 #define SICR_TXC_INACTIVE BIT12
603 #define SICR_TXC (BIT13+BIT12)
1876 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
4757 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4779 RegValue |= BIT12;
4821 RegValue |= ( BIT12 | BIT10 | BIT9 );
4896 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
5215 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; brea
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H A Dsynclink_gt.c426 #define IRQ_TXIDLE BIT12
4137 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4138 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4139 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4140 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4201 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4202 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4203 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4204 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c305 #define IRQ_UNDERRUN BIT12 // transmit data underrun

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