Searched refs:pChipcHw (Results 1 - 5 of 5) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/
H A DchipcHw_inline.h50 return pChipcHw->ChipId;
62 if ((pChipcHw->
96 return (pChipcHw->
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
128 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
159 return pChipcHw->BusIntfClock;
175 reg32_modify_or(&pChipcHw->AudioEnable, mask);
191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
218 pChipcHw
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H A DchipcHw_reg.h134 #define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) macro
257 #define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
280 #define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
287 #define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
299 #define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
307 #define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
314 #define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-bcmring/csp/chipc/
H A DchipcHw.c73 if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
78 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
89 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
95 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
100 pPLLReg = &pChipcHw->DDRClock;
104 pPLLReg = &pChipcHw->ARMClock;
108 pPLLReg = &pChipcHw->ESWClock;
112 pPLLReg = &pChipcHw->VPMClock;
116 pPLLReg = &pChipcHw->ESW125Clock;
120 pPLLReg = &pChipcHw
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H A DchipcHw_init.c76 pChipcHw->PLLConfig2 =
90 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
93 pChipcHw->PLLPreDivider2 = pllPreDivider2;
95 pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
98 pChipcHw->PLLControl12 = 0x38000700;
99 pChipcHw->PLLControl22 = 0x00000015;
103 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
108 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
122 pChipcHw->PLLConfig2 &=
131 while (!(pChipcHw
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H A DchipcHw_reset.c53 pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
54 pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;

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