Lines Matching refs:pChipcHw
76 pChipcHw->PLLConfig2 =
90 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
93 pChipcHw->PLLPreDivider2 = pllPreDivider2;
95 pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
98 pChipcHw->PLLControl12 = 0x38000700;
99 pChipcHw->PLLControl22 = 0x00000015;
103 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
108 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
122 pChipcHw->PLLConfig2 &=
131 while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
137 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
160 pChipcHw->PLLConfig =
185 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
188 pChipcHw->PLLPreDivider = pllPreDivider;
191 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
194 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
200 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
205 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
219 pChipcHw->PLLConfig &=
226 while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
227 || !(pChipcHw->
234 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
270 pChipcHw->ACLKClock =
271 (pChipcHw->