Lines Matching refs:pChipcHw
50 return pChipcHw->ChipId;
62 if ((pChipcHw->
96 return (pChipcHw->
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
128 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
159 return pChipcHw->BusIntfClock;
175 reg32_modify_or(&pChipcHw->AudioEnable, mask);
191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
218 pChipcHw->SoftReset1 ^= ctrl1;
219 pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
230 pChipcHw->SoftReset1 |= ctrl1;
232 pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
249 pChipcHw->SoftReset1 &= ~unhold;
267 reg32_write(&pChipcHw->MiscCtrl, mask);
272 reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
277 reg32_modify_or(&pChipcHw->MiscCtrl, mask);
296 reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
297 reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
310 return pChipcHw->Sticky;
331 sticky = pChipcHw->Sticky;
358 pChipcHw->Sticky = bits;
380 uint32_t sticky = pChipcHw->Sticky;
413 pChipcHw->Sticky = bits | mask;
429 return pChipcHw->SoftStraps;
444 reg32_write(&pChipcHw->SoftStraps, strapOptions);
459 return pChipcHw->PinStraps;
598 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
621 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
637 reg32_write(&pChipcHw->LcdPifMode, 0);
650 reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
663 reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
787 reg32_modify_and(&pChipcHw->MiscCtrl,
801 reg32_modify_or(&pChipcHw->MiscCtrl,
815 reg32_modify_or(&pChipcHw->MiscCtrl,
829 reg32_modify_and(&pChipcHw->MiscCtrl,
849 pPLLReg = &pChipcHw->DDRClock;
852 pPLLReg = &pChipcHw->ARMClock;
855 pPLLReg = &pChipcHw->ESWClock;
858 pPLLReg = &pChipcHw->VPMClock;
861 pPLLReg = &pChipcHw->ESW125Clock;
864 pPLLReg = &pChipcHw->UARTClock;
867 pPLLReg = &pChipcHw->SDIO0Clock;
870 pPLLReg = &pChipcHw->SDIO1Clock;
873 pPLLReg = &pChipcHw->SPIClock;
876 pPLLReg = &pChipcHw->ETMClock;
879 pPLLReg = &pChipcHw->USBClock;
891 pPLLReg = &pChipcHw->LCDClock;
903 pPLLReg = &pChipcHw->APMClock;
915 pClockCtrl = &pChipcHw->ACLKClock;
918 pClockCtrl = &pChipcHw->OTPClock;
921 pClockCtrl = &pChipcHw->I2CClock;
924 pClockCtrl = &pChipcHw->I2S0Clock;
927 pClockCtrl = &pChipcHw->RTBUSClock;
930 pClockCtrl = &pChipcHw->APM100Clock;
933 pClockCtrl = &pChipcHw->TSCClock;
936 pClockCtrl = &pChipcHw->LEDClock;
939 pClockCtrl = &pChipcHw->I2S1Clock;
1074 return pChipcHw->SoftStraps & 0x00000001;
1083 reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1092 reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1101 reg32_modify_or(&pChipcHw->PLLConfig,
1111 reg32_modify_or(&pChipcHw->PLLConfig2,
1121 reg32_modify_and(&pChipcHw->PLLConfig,
1131 reg32_modify_and(&pChipcHw->PLLConfig2,
1141 return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1150 return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1160 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1161 pChipcHw->PLLConfig |=
1174 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1175 pChipcHw->PLLConfig2 |=
1186 return (uint8_t) ((pChipcHw->
1197 return (uint8_t) ((pChipcHw->
1211 pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1224 pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1264 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1266 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1268 pChipcHw->VPMPhaseCtrl2 =
1269 (pChipcHw->
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1336 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1349 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1362 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1375 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1409 pChipcHw->DDRPhaseCtrl1 &=
1415 pChipcHw->DDRPhaseCtrl1 |=
1453 pChipcHw->VPMPhaseCtrl1 &=
1459 pChipcHw->VPMPhaseCtrl1 |=
1477 return (pChipcHw->
1491 return (pChipcHw->
1503 return (pChipcHw->
1516 return (pChipcHw->
1529 return (pChipcHw->
1542 return (pChipcHw->
1558 pChipcHw->DDRPhaseCtrl2 &=
1561 pChipcHw->DDRPhaseCtrl2 |=
1578 pChipcHw->VPMPhaseCtrl2 &=
1581 pChipcHw->VPMPhaseCtrl2 |=
1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1612 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1613 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1643 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1669 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;