/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7366.c | 123 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_ [all...] |
H A D | clock-sh7724.c | 149 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 170 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 172 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 173 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 174 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_ [all...] |
H A D | clock-sh7786.c | 73 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 95 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 103 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_ [all...] |
H A D | clock-sh7723.c | 123 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_S [all...] |
H A D | clock-sh7343.c | 120 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 159 [MSTP020] = MSTP(&div4_clks[DIV4_ [all...] |
H A D | clock-sh7722.c | 122 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT), 152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0), 156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_ [all...] |
H A D | clock-sh7785.c | 72 struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_ [all...] |
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-shmobile/ |
H A D | clock-sh7367.c | 182 static struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */ 234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */ 235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */ 236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */ 237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */ 239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */ 241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */ 255 [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */ 256 [SYMSTP214] = MSTP(&div4_clks[DIV4_H [all...] |
H A D | clock-sh7377.c | 192 static struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 244 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ 245 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ 246 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ 247 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ 249 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ 250 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ 264 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */ 265 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ 266 [MSTP313] = MSTP(&div4_clks[DIV4_H [all...] |
H A D | clock-sh7372.c | 341 static struct clk div4_clks[DIV4_NR] = { variable in typeref:struct:clk 411 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ 412 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ 413 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ 414 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ 415 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ 416 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ 417 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ 418 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ 420 [MSTP106] = MSTP(&div4_clks[DIV4_ [all...] |