Lines Matching refs:div4_clks
123 struct clk div4_clks[DIV4_NR] = {
154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
169 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
170 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
171 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
172 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
173 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
174 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
211 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
212 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);