Lines Matching refs:div4_clks
149 struct clk div4_clks[DIV4_NR] = {
168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
173 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
174 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
177 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
178 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
180 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
183 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
184 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
185 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
186 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
187 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
188 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
189 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
190 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
191 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
192 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
196 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
197 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
199 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
201 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
202 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
203 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
204 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
205 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
206 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
207 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
208 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
209 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
210 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
211 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
212 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
213 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
214 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
215 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
216 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
217 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
218 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
219 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
220 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
221 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
238 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
239 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);