Searched refs:cx_set (Results 1 - 21 of 21) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/video/cx23885/
H A Dcx23885-cards.c721 cx_set(GP0_IO, bitmask);
732 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
739 cx_set(GP0_IO, 0x00050000);
744 cx_set(GP0_IO, 0x00050005);
749 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
787 cx_set(GP0_IO, 0x00050000);
791 cx_set(GP0_IO, 0x00050005);
808 cx_set(GP0_IO, 0x00050000);
812 cx_set(GP0_IO, 0x00050005);
820 cx_set(GP0_I
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H A Dcx23885-vbi.c78 cx_set(VID_A_INT_MSK, 0x000022);
81 cx_set(DEV_CNTRL2, (1<<5));
82 cx_set(VID_A_DMA_CTL, 0x00000022);
H A Dcx23885-core.c300 cx_set(PCI_INT_MSK, mask);
313 cx_set(PCI_INT_MSK, v);
1353 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1354 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1362 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1909 cx_set(GP0_IO, mask & 0x7);
1916 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1965 cx_set(GP0_IO, (mask & 0x7) << 16);
1981 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
H A Dcimax2.c164 cx_set(MC417_RWD, NETUP_CTRL_OFF);
H A Dcx23885.h455 #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) macro
H A Dcx23885-video.c445 cx_set(VID_A_INT_MSK, 0x000011);
448 cx_set(DEV_CNTRL2, (1<<5));
449 cx_set(VID_A_DMA_CTL, 0x11); /* FIFO and RISC enable */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/video/cx88/
H A Dcx88-vbi.c68 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
69 cx_set(MO_VID_INTMSK, 0x0f0088);
72 cx_set(VID_CAPTURE_CONTROL,0x18);
75 cx_set(MO_DEV_CNTRL2, (1<<5));
76 cx_set(MO_VID_DMACNTRL, 0x88);
H A Dcx88-dvb.c338 cx_set(MO_GP0_IO, 8);
431 cx_set(MO_GP0_IO, 0x6040);
437 cx_set(MO_GP0_IO, 0x20);
769 cx_set(MO_GP0_IO, 0x0800);
773 cx_set(MO_GP0_IO, 0x08);
798 cx_set(MO_GP0_IO, 0x8000);
1088 cx_set(MO_GP0_IO, 1);
1109 cx_set(MO_GP0_IO, 9);
1127 cx_set(MO_GP0_IO, 1);
1148 cx_set(MO_GP0_I
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H A Dcx88-cards.c2657 cx_set(MO_GP0_IO, 0x008989FF);
2730 cx_set(MO_GP0_IO, 0x00001000);
2733 cx_set(MO_GP0_IO, 0x00000010);
2739 cx_set(MO_GP0_IO, 0x101010);
2786 cx_set(MO_GP1_IO, 0x1010);
2790 cx_set(MO_GP1_IO, 0x10);
2937 cx_set(MO_GP0_IO, 0x00000010);
3028 cx_set(MO_GP0_IO, 0x00000088); /* 702 out of reset */
3044 cx_set(MO_GP0_IO, 0x00001010);
3054 cx_set(MO_GP0_I
[all...]
H A Dcx88-mpeg.c166 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_TSINT);
167 cx_set(MO_TS_INTMSK, 0x1f0011);
170 cx_set(MO_DEV_CNTRL2, (1<<5));
171 cx_set(MO_TS_DMACNTRL, 0x11);
496 cx_set(MO_PCI_INTMSK, core->pci_irqmask);
H A Dcx88-alsa.c161 cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT);
164 cx_set(MO_DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */
165 cx_set(MO_AUD_DMACNTRL, 0x11); /* audio downstream FIFO and RISC enable */
H A Dcx88-video.c407 cx_set(MO_AFECFG_IO, 0x00000001);
408 cx_set(MO_INPUT_FORMAT, 0x00010010);
409 cx_set(MO_FILTER_EVEN, 0x00002020);
410 cx_set(MO_FILTER_ODD, 0x00002020);
469 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
478 cx_set(MO_VID_INTMSK, 0x0f0011);
481 cx_set(VID_CAPTURE_CONTROL,0x06);
484 cx_set(MO_DEV_CNTRL2, (1<<5));
485 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */
1867 cx_set(MO_PCI_INTMS
[all...]
H A Dcx88-blackbird.c1232 cx_set(MO_GP0_IO, 0x00000080);
1236 cx_set(MO_GP0_IO, 0x00000080);
1239 cx_set(MO_GP0_IO, 0x00000004);
H A Dcx88.h549 #define cx_set(reg,bit) cx_andor((reg),(bit),(bit)) macro
H A Dcx88-tvaudio.c149 cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/cx25821/
H A Dcx25821-alsa.c193 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
197 cx_set(AUD_INT_DMA_CTL,
H A Dcx25821-audio-upstream.c693 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
708 cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en);
H A Dcx25821-video-upstream-ch2.c718 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
732 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
H A Dcx25821.h517 #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) macro
H A Dcx25821-video-upstream.c770 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
785 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
H A Dcx25821-video.c298 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i));
299 cx_set(channel->int_msk, 0x11);
522 cx_set(PCI_INT_MSK, 0xff);

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