1/* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include "cx25821-video.h" 24#include "cx25821-video-upstream.h" 25 26#include <linux/fs.h> 27#include <linux/errno.h> 28#include <linux/kernel.h> 29#include <linux/init.h> 30#include <linux/module.h> 31#include <linux/syscalls.h> 32#include <linux/file.h> 33#include <linux/fcntl.h> 34#include <linux/slab.h> 35#include <linux/uaccess.h> 36 37MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); 38MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); 39MODULE_LICENSE("GPL"); 40 41static int _intr_msk = 42 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR; 43 44int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev, 45 struct sram_channel *ch, 46 unsigned int bpl, u32 risc) 47{ 48 unsigned int i, lines; 49 u32 cdt; 50 51 if (ch->cmds_start == 0) { 52 cx_write(ch->ptr1_reg, 0); 53 cx_write(ch->ptr2_reg, 0); 54 cx_write(ch->cnt2_reg, 0); 55 cx_write(ch->cnt1_reg, 0); 56 return 0; 57 } 58 59 bpl = (bpl + 7) & ~7; /* alignment */ 60 cdt = ch->cdt; 61 lines = ch->fifo_size / bpl; 62 63 if (lines > 4) 64 lines = 4; 65 66 BUG_ON(lines < 2); 67 68 /* write CDT */ 69 for (i = 0; i < lines; i++) { 70 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 71 cx_write(cdt + 16 * i + 4, 0); 72 cx_write(cdt + 16 * i + 8, 0); 73 cx_write(cdt + 16 * i + 12, 0); 74 } 75 76 /* write CMDS */ 77 cx_write(ch->cmds_start + 0, risc); 78 79 cx_write(ch->cmds_start + 4, 0); 80 cx_write(ch->cmds_start + 8, cdt); 81 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 82 cx_write(ch->cmds_start + 16, ch->ctrl_start); 83 84 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW); 85 86 for (i = 24; i < 80; i += 4) 87 cx_write(ch->cmds_start + i, 0); 88 89 /* fill registers */ 90 cx_write(ch->ptr1_reg, ch->fifo_start); 91 cx_write(ch->ptr2_reg, cdt); 92 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 93 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 94 95 return 0; 96} 97 98static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev, 99 __le32 *rp, unsigned int offset, 100 unsigned int bpl, u32 sync_line, 101 unsigned int lines, int fifo_enable, 102 int field_type) 103{ 104 unsigned int line, i; 105 int dist_betwn_starts = bpl * 2; 106 107 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 108 109 if (USE_RISC_NOOP_VIDEO) { 110 for (i = 0; i < NUM_NO_OPS; i++) 111 *(rp++) = cpu_to_le32(RISC_NOOP); 112 } 113 114 /* scan lines */ 115 for (line = 0; line < lines; line++) { 116 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); 117 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset); 118 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 119 120 if ((lines <= NTSC_FIELD_HEIGHT) 121 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) { 122 offset += dist_betwn_starts; 123 } 124 } 125 126 return rp; 127} 128 129static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp, 130 dma_addr_t databuf_phys_addr, 131 unsigned int offset, u32 sync_line, 132 unsigned int bpl, unsigned int lines, 133 int fifo_enable, int field_type) 134{ 135 unsigned int line, i; 136 struct sram_channel *sram_ch = 137 dev->channels[dev->_channel_upstream_select].sram_channels; 138 int dist_betwn_starts = bpl * 2; 139 140 /* sync instruction */ 141 if (sync_line != NO_SYNC_LINE) 142 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 143 144 if (USE_RISC_NOOP_VIDEO) { 145 for (i = 0; i < NUM_NO_OPS; i++) 146 *(rp++) = cpu_to_le32(RISC_NOOP); 147 } 148 149 /* scan lines */ 150 for (line = 0; line < lines; line++) { 151 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); 152 *(rp++) = cpu_to_le32(databuf_phys_addr + offset); 153 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 154 155 if ((lines <= NTSC_FIELD_HEIGHT) 156 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) 157 /* to skip the other field line */ 158 offset += dist_betwn_starts; 159 160 /* check if we need to enable the FIFO after the first 4 lines 161 * For the upstream video channel, the risc engine will enable 162 * the FIFO. */ 163 if (fifo_enable && line == 3) { 164 *(rp++) = RISC_WRITECR; 165 *(rp++) = sram_ch->dma_ctl; 166 *(rp++) = FLD_VID_FIFO_EN; 167 *(rp++) = 0x00000001; 168 } 169 } 170 171 return rp; 172} 173 174int cx25821_risc_buffer_upstream(struct cx25821_dev *dev, 175 struct pci_dev *pci, 176 unsigned int top_offset, 177 unsigned int bpl, unsigned int lines) 178{ 179 __le32 *rp; 180 int fifo_enable = 0; 181 /* get line count for single field */ 182 int singlefield_lines = lines >> 1; 183 int odd_num_lines = singlefield_lines; 184 int frame = 0; 185 int frame_size = 0; 186 int databuf_offset = 0; 187 int risc_program_size = 0; 188 int risc_flag = RISC_CNT_RESET; 189 unsigned int bottom_offset = bpl; 190 dma_addr_t risc_phys_jump_addr; 191 192 if (dev->_isNTSC) { 193 odd_num_lines = singlefield_lines + 1; 194 risc_program_size = FRAME1_VID_PROG_SIZE; 195 frame_size = 196 (bpl == 197 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : 198 FRAME_SIZE_NTSC_Y422; 199 } else { 200 risc_program_size = PAL_VID_PROG_SIZE; 201 frame_size = 202 (bpl == 203 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 204 } 205 206 /* Virtual address of Risc buffer program */ 207 rp = dev->_dma_virt_addr; 208 209 for (frame = 0; frame < NUM_FRAMES; frame++) { 210 databuf_offset = frame_size * frame; 211 212 if (UNSET != top_offset) { 213 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; 214 rp = cx25821_risc_field_upstream(dev, rp, 215 dev-> 216 _data_buf_phys_addr + 217 databuf_offset, 218 top_offset, 0, bpl, 219 odd_num_lines, 220 fifo_enable, 221 ODD_FIELD); 222 } 223 224 fifo_enable = FIFO_DISABLE; 225 226 /* Even Field */ 227 rp = cx25821_risc_field_upstream(dev, rp, 228 dev->_data_buf_phys_addr + 229 databuf_offset, bottom_offset, 230 0x200, bpl, singlefield_lines, 231 fifo_enable, EVEN_FIELD); 232 233 if (frame == 0) { 234 risc_flag = RISC_CNT_RESET; 235 risc_phys_jump_addr = 236 dev->_dma_phys_start_addr + risc_program_size; 237 } else { 238 risc_phys_jump_addr = dev->_dma_phys_start_addr; 239 risc_flag = RISC_CNT_INC; 240 } 241 242 /* Loop to 2ndFrameRISC or to Start of Risc 243 * program & generate IRQ 244 */ 245 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); 246 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 247 *(rp++) = cpu_to_le32(0); 248 } 249 250 return 0; 251} 252 253void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev) 254{ 255 struct sram_channel *sram_ch = 256 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels; 257 u32 tmp = 0; 258 259 if (!dev->_is_running) { 260 printk 261 (KERN_INFO "cx25821: No video file is currently running so return!\n"); 262 return; 263 } 264 /* Disable RISC interrupts */ 265 tmp = cx_read(sram_ch->int_msk); 266 cx_write(sram_ch->int_msk, tmp & ~_intr_msk); 267 268 /* Turn OFF risc and fifo enable */ 269 tmp = cx_read(sram_ch->dma_ctl); 270 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN)); 271 272 /* Clear data buffer memory */ 273 if (dev->_data_buf_virt_addr) 274 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size); 275 276 dev->_is_running = 0; 277 dev->_is_first_frame = 0; 278 dev->_frame_count = 0; 279 dev->_file_status = END_OF_FILE; 280 281 if (dev->_irq_queues) { 282 kfree(dev->_irq_queues); 283 dev->_irq_queues = NULL; 284 } 285 286 if (dev->_filename != NULL) 287 kfree(dev->_filename); 288 289 tmp = cx_read(VID_CH_MODE_SEL); 290 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 291} 292 293void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev) 294{ 295 if (dev->_is_running) 296 cx25821_stop_upstream_video_ch1(dev); 297 298 if (dev->_dma_virt_addr) { 299 pci_free_consistent(dev->pci, dev->_risc_size, 300 dev->_dma_virt_addr, dev->_dma_phys_addr); 301 dev->_dma_virt_addr = NULL; 302 } 303 304 if (dev->_data_buf_virt_addr) { 305 pci_free_consistent(dev->pci, dev->_data_buf_size, 306 dev->_data_buf_virt_addr, 307 dev->_data_buf_phys_addr); 308 dev->_data_buf_virt_addr = NULL; 309 } 310} 311 312int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch) 313{ 314 struct file *myfile; 315 int frame_index_temp = dev->_frame_index; 316 int i = 0; 317 int line_size = 318 (dev->_pixel_format == 319 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 320 int frame_size = 0; 321 int frame_offset = 0; 322 ssize_t vfs_read_retval = 0; 323 char mybuf[line_size]; 324 loff_t file_offset; 325 loff_t pos; 326 mm_segment_t old_fs; 327 328 if (dev->_file_status == END_OF_FILE) 329 return 0; 330 331 if (dev->_isNTSC) { 332 frame_size = 333 (line_size == 334 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : 335 FRAME_SIZE_NTSC_Y422; 336 } else { 337 frame_size = 338 (line_size == 339 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 340 } 341 342 frame_offset = (frame_index_temp > 0) ? frame_size : 0; 343 file_offset = dev->_frame_count * frame_size; 344 345 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0); 346 347 if (IS_ERR(myfile)) { 348 const int open_errno = -PTR_ERR(myfile); 349 printk(KERN_ERR 350 "%s(): ERROR opening file(%s) with errno = %d!\n", 351 __func__, dev->_filename, open_errno); 352 return PTR_ERR(myfile); 353 } else { 354 if (!(myfile->f_op)) { 355 printk(KERN_ERR 356 "%s: File has no file operations registered!", 357 __func__); 358 filp_close(myfile, NULL); 359 return -EIO; 360 } 361 362 if (!myfile->f_op->read) { 363 printk(KERN_ERR 364 "%s: File has no READ operations registered!", 365 __func__); 366 filp_close(myfile, NULL); 367 return -EIO; 368 } 369 370 pos = myfile->f_pos; 371 old_fs = get_fs(); 372 set_fs(KERNEL_DS); 373 374 for (i = 0; i < dev->_lines_count; i++) { 375 pos = file_offset; 376 377 vfs_read_retval = 378 vfs_read(myfile, mybuf, line_size, &pos); 379 380 if (vfs_read_retval > 0 && vfs_read_retval == line_size 381 && dev->_data_buf_virt_addr != NULL) { 382 memcpy((void *)(dev->_data_buf_virt_addr + 383 frame_offset / 4), mybuf, 384 vfs_read_retval); 385 } 386 387 file_offset += vfs_read_retval; 388 frame_offset += vfs_read_retval; 389 390 if (vfs_read_retval < line_size) { 391 printk(KERN_INFO 392 "Done: exit %s() since no more bytes to \ 393 read from Video file.\n", 394 __func__); 395 break; 396 } 397 } 398 399 if (i > 0) 400 dev->_frame_count++; 401 402 dev->_file_status = 403 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 404 405 set_fs(old_fs); 406 filp_close(myfile, NULL); 407 } 408 409 return 0; 410} 411 412static void cx25821_vidups_handler(struct work_struct *work) 413{ 414 struct cx25821_dev *dev = 415 container_of(work, struct cx25821_dev, _irq_work_entry); 416 417 if (!dev) { 418 printk(KERN_ERR 419 "ERROR %s(): since container_of(work_struct) FAILED!\n", 420 __func__); 421 return; 422 } 423 424 cx25821_get_frame(dev, 425 dev->channels[dev->_channel_upstream_select]. 426 sram_channels); 427} 428 429int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch) 430{ 431 struct file *myfile; 432 int i = 0, j = 0; 433 int line_size = 434 (dev->_pixel_format == 435 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ; 436 ssize_t vfs_read_retval = 0; 437 char mybuf[line_size]; 438 loff_t pos; 439 loff_t offset = (unsigned long)0; 440 mm_segment_t old_fs; 441 442 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0); 443 444 if (IS_ERR(myfile)) { 445 const int open_errno = -PTR_ERR(myfile); 446 printk(KERN_ERR "%s(): ERROR opening file(%s) with errno = %d!\n", 447 __func__, dev->_filename, open_errno); 448 return PTR_ERR(myfile); 449 } else { 450 if (!(myfile->f_op)) { 451 printk(KERN_ERR 452 "%s: File has no file operations registered!", 453 __func__); 454 filp_close(myfile, NULL); 455 return -EIO; 456 } 457 458 if (!myfile->f_op->read) { 459 printk(KERN_ERR 460 "%s: File has no READ operations registered! \ 461 Returning.", 462 __func__); 463 filp_close(myfile, NULL); 464 return -EIO; 465 } 466 467 pos = myfile->f_pos; 468 old_fs = get_fs(); 469 set_fs(KERNEL_DS); 470 471 for (j = 0; j < NUM_FRAMES; j++) { 472 for (i = 0; i < dev->_lines_count; i++) { 473 pos = offset; 474 475 vfs_read_retval = 476 vfs_read(myfile, mybuf, line_size, &pos); 477 478 if (vfs_read_retval > 0 479 && vfs_read_retval == line_size 480 && dev->_data_buf_virt_addr != NULL) { 481 memcpy((void *)(dev-> 482 _data_buf_virt_addr + 483 offset / 4), mybuf, 484 vfs_read_retval); 485 } 486 487 offset += vfs_read_retval; 488 489 if (vfs_read_retval < line_size) { 490 printk(KERN_INFO 491 "Done: exit %s() since no more \ 492 bytes to read from Video file.\n", 493 __func__); 494 break; 495 } 496 } 497 498 if (i > 0) 499 dev->_frame_count++; 500 501 if (vfs_read_retval < line_size) 502 break; 503 } 504 505 dev->_file_status = 506 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE; 507 508 set_fs(old_fs); 509 myfile->f_pos = 0; 510 filp_close(myfile, NULL); 511 } 512 513 return 0; 514} 515 516int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev, 517 struct sram_channel *sram_ch, int bpl) 518{ 519 int ret = 0; 520 dma_addr_t dma_addr; 521 dma_addr_t data_dma_addr; 522 523 if (dev->_dma_virt_addr != NULL) { 524 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size, 525 dev->_dma_virt_addr, dev->_dma_phys_addr); 526 } 527 528 dev->_dma_virt_addr = 529 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size, 530 &dma_addr); 531 dev->_dma_virt_start_addr = dev->_dma_virt_addr; 532 dev->_dma_phys_start_addr = dma_addr; 533 dev->_dma_phys_addr = dma_addr; 534 dev->_risc_size = dev->upstream_riscbuf_size; 535 536 if (!dev->_dma_virt_addr) { 537 printk 538 (KERN_ERR "cx25821: FAILED to allocate memory for Risc \ 539 buffer! Returning.\n"); 540 return -ENOMEM; 541 } 542 543 /* Clear memory at address */ 544 memset(dev->_dma_virt_addr, 0, dev->_risc_size); 545 546 if (dev->_data_buf_virt_addr != NULL) { 547 pci_free_consistent(dev->pci, dev->upstream_databuf_size, 548 dev->_data_buf_virt_addr, 549 dev->_data_buf_phys_addr); 550 } 551 /* For Video Data buffer allocation */ 552 dev->_data_buf_virt_addr = 553 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size, 554 &data_dma_addr); 555 dev->_data_buf_phys_addr = data_dma_addr; 556 dev->_data_buf_size = dev->upstream_databuf_size; 557 558 if (!dev->_data_buf_virt_addr) { 559 printk 560 (KERN_ERR "cx25821: FAILED to allocate memory for data \ 561 buffer! Returning.\n"); 562 return -ENOMEM; 563 } 564 565 /* Clear memory at address */ 566 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size); 567 568 ret = cx25821_openfile(dev, sram_ch); 569 if (ret < 0) 570 return ret; 571 572 /* Create RISC programs */ 573 ret = 574 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl, 575 dev->_lines_count); 576 if (ret < 0) { 577 printk(KERN_INFO 578 "cx25821: Failed creating Video Upstream Risc programs!\n"); 579 goto error; 580 } 581 582 return 0; 583 584error: 585 return ret; 586} 587 588int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num, 589 u32 status) 590{ 591 u32 int_msk_tmp; 592 struct sram_channel *channel = dev->channels[chan_num].sram_channels; 593 int singlefield_lines = NTSC_FIELD_HEIGHT; 594 int line_size_in_bytes = Y422_LINE_SZ; 595 int odd_risc_prog_size = 0; 596 dma_addr_t risc_phys_jump_addr; 597 __le32 *rp; 598 599 if (status & FLD_VID_SRC_RISC1) { 600 /* We should only process one program per call */ 601 u32 prog_cnt = cx_read(channel->gpcnt); 602 603 /* Since we've identified our IRQ, clear our bits from the 604 * interrupt mask and interrupt status registers */ 605 int_msk_tmp = cx_read(channel->int_msk); 606 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); 607 cx_write(channel->int_stat, _intr_msk); 608 609 spin_lock(&dev->slock); 610 611 dev->_frame_index = prog_cnt; 612 613 queue_work(dev->_irq_queues, &dev->_irq_work_entry); 614 615 if (dev->_is_first_frame) { 616 dev->_is_first_frame = 0; 617 618 if (dev->_isNTSC) { 619 singlefield_lines += 1; 620 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; 621 } else { 622 singlefield_lines = PAL_FIELD_HEIGHT; 623 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; 624 } 625 626 if (dev->_dma_virt_start_addr != NULL) { 627 line_size_in_bytes = 628 (dev->_pixel_format == 629 PIXEL_FRMT_411) ? Y411_LINE_SZ : 630 Y422_LINE_SZ; 631 risc_phys_jump_addr = 632 dev->_dma_phys_start_addr + 633 odd_risc_prog_size; 634 635 rp = cx25821_update_riscprogram(dev, 636 dev-> 637 _dma_virt_start_addr, 638 TOP_OFFSET, 639 line_size_in_bytes, 640 0x0, 641 singlefield_lines, 642 FIFO_DISABLE, 643 ODD_FIELD); 644 645 /* Jump to Even Risc program of 1st Frame */ 646 *(rp++) = cpu_to_le32(RISC_JUMP); 647 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 648 *(rp++) = cpu_to_le32(0); 649 } 650 } 651 652 spin_unlock(&dev->slock); 653 } else { 654 if (status & FLD_VID_SRC_UF) 655 printk 656 (KERN_ERR "%s: Video Received Underflow Error \ 657 Interrupt!\n", __func__); 658 659 if (status & FLD_VID_SRC_SYNC) 660 printk(KERN_ERR "%s: Video Received Sync Error \ 661 Interrupt!\n", __func__); 662 663 if (status & FLD_VID_SRC_OPC_ERR) 664 printk(KERN_ERR "%s: Video Received OpCode Error \ 665 Interrupt!\n", __func__); 666 } 667 668 if (dev->_file_status == END_OF_FILE) { 669 printk(KERN_ERR "cx25821: EOF Channel 1 Framecount = %d\n", 670 dev->_frame_count); 671 return -1; 672 } 673 /* ElSE, set the interrupt mask register, re-enable irq. */ 674 int_msk_tmp = cx_read(channel->int_msk); 675 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); 676 677 return 0; 678} 679 680static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id) 681{ 682 struct cx25821_dev *dev = dev_id; 683 u32 msk_stat, vid_status; 684 int handled = 0; 685 int channel_num = 0; 686 struct sram_channel *sram_ch; 687 688 if (!dev) 689 return -1; 690 691 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I; 692 693 sram_ch = dev->channels[channel_num].sram_channels; 694 695 msk_stat = cx_read(sram_ch->int_mstat); 696 vid_status = cx_read(sram_ch->int_stat); 697 698 /* Only deal with our interrupt */ 699 if (vid_status) { 700 handled = 701 cx25821_video_upstream_irq(dev, channel_num, vid_status); 702 } 703 704 if (handled < 0) 705 cx25821_stop_upstream_video_ch1(dev); 706 else 707 handled += handled; 708 709 return IRQ_RETVAL(handled); 710} 711 712void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch, 713 int pix_format) 714{ 715 int width = WIDTH_D1; 716 int height = dev->_lines_count; 717 int num_lines, odd_num_lines; 718 u32 value; 719 int vip_mode = OUTPUT_FRMT_656; 720 721 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7); 722 value &= 0xFFFFFFEF; 723 value |= dev->_isNTSC ? 0 : 0x10; 724 cx_write(ch->vid_fmt_ctl, value); 725 726 /* set number of active pixels in each line. 727 * Default is 720 pixels in both NTSC and PAL format */ 728 cx_write(ch->vid_active_ctl1, width); 729 730 num_lines = (height / 2) & 0x3FF; 731 odd_num_lines = num_lines; 732 733 if (dev->_isNTSC) 734 odd_num_lines += 1; 735 736 value = (num_lines << 16) | odd_num_lines; 737 738 /* set number of active lines in field 0 (top) and field 1 (bottom) */ 739 cx_write(ch->vid_active_ctl2, value); 740 741 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3); 742} 743 744int cx25821_start_video_dma_upstream(struct cx25821_dev *dev, 745 struct sram_channel *sram_ch) 746{ 747 u32 tmp = 0; 748 int err = 0; 749 750 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 751 * channel A-C 752 */ 753 tmp = cx_read(VID_CH_MODE_SEL); 754 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); 755 756 /* Set the physical start address of the RISC program in the initial 757 * program counter(IPC) member of the cmds. 758 */ 759 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr); 760 /* Risc IPC High 64 bits 63-32 */ 761 cx_write(sram_ch->cmds_start + 4, 0); 762 763 /* reset counter */ 764 cx_write(sram_ch->gpcnt_ctl, 3); 765 766 /* Clear our bits from the interrupt status register. */ 767 cx_write(sram_ch->int_stat, _intr_msk); 768 769 /* Set the interrupt mask register, enable irq. */ 770 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); 771 tmp = cx_read(sram_ch->int_msk); 772 cx_write(sram_ch->int_msk, tmp |= _intr_msk); 773 774 err = 775 request_irq(dev->pci->irq, cx25821_upstream_irq, 776 IRQF_SHARED | IRQF_DISABLED, dev->name, dev); 777 if (err < 0) { 778 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, 779 dev->pci->irq); 780 goto fail_irq; 781 } 782 783 /* Start the DMA engine */ 784 tmp = cx_read(sram_ch->dma_ctl); 785 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); 786 787 dev->_is_running = 1; 788 dev->_is_first_frame = 1; 789 790 return 0; 791 792fail_irq: 793 cx25821_dev_unregister(dev); 794 return err; 795} 796 797int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select, 798 int pixel_format) 799{ 800 struct sram_channel *sram_ch; 801 u32 tmp; 802 int retval = 0; 803 int err = 0; 804 int data_frame_size = 0; 805 int risc_buffer_size = 0; 806 int str_length = 0; 807 808 if (dev->_is_running) { 809 printk(KERN_INFO "Video Channel is still running so return!\n"); 810 return 0; 811 } 812 813 dev->_channel_upstream_select = channel_select; 814 sram_ch = dev->channels[channel_select].sram_channels; 815 816 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler); 817 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue"); 818 819 if (!dev->_irq_queues) { 820 printk 821 (KERN_ERR "cx25821: create_singlethread_workqueue() for \ 822 Video FAILED!\n"); 823 return -ENOMEM; 824 } 825 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 826 * channel A-C 827 */ 828 tmp = cx_read(VID_CH_MODE_SEL); 829 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); 830 831 dev->_is_running = 0; 832 dev->_frame_count = 0; 833 dev->_file_status = RESET_STATUS; 834 dev->_lines_count = dev->_isNTSC ? 480 : 576; 835 dev->_pixel_format = pixel_format; 836 dev->_line_size = 837 (dev->_pixel_format == 838 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 839 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; 840 risc_buffer_size = 841 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; 842 843 if (dev->input_filename) { 844 str_length = strlen(dev->input_filename); 845 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL); 846 847 if (!dev->_filename) 848 goto error; 849 850 memcpy(dev->_filename, dev->input_filename, str_length + 1); 851 } else { 852 str_length = strlen(dev->_defaultname); 853 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL); 854 855 if (!dev->_filename) 856 goto error; 857 858 memcpy(dev->_filename, dev->_defaultname, str_length + 1); 859 } 860 861 /* Default if filename is empty string */ 862 if (strcmp(dev->input_filename, "") == 0) { 863 if (dev->_isNTSC) { 864 dev->_filename = 865 (dev->_pixel_format == 866 PIXEL_FRMT_411) ? "/root/vid411.yuv" : 867 "/root/vidtest.yuv"; 868 } else { 869 dev->_filename = 870 (dev->_pixel_format == 871 PIXEL_FRMT_411) ? "/root/pal411.yuv" : 872 "/root/pal422.yuv"; 873 } 874 } 875 876 dev->_is_running = 0; 877 dev->_frame_count = 0; 878 dev->_file_status = RESET_STATUS; 879 dev->_lines_count = dev->_isNTSC ? 480 : 576; 880 dev->_pixel_format = pixel_format; 881 dev->_line_size = 882 (dev->_pixel_format == 883 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 884 885 retval = 886 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size, 887 0); 888 889 /* setup fifo + format */ 890 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format); 891 892 dev->upstream_riscbuf_size = risc_buffer_size * 2; 893 dev->upstream_databuf_size = data_frame_size * 2; 894 895 /* Allocating buffers and prepare RISC program */ 896 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size); 897 if (retval < 0) { 898 printk(KERN_ERR 899 "%s: Failed to set up Video upstream buffers!\n", 900 dev->name); 901 goto error; 902 } 903 904 cx25821_start_video_dma_upstream(dev, sram_ch); 905 906 return 0; 907 908error: 909 cx25821_dev_unregister(dev); 910 911 return err; 912} 913