1/* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#include <linux/pci.h> 23#include <linux/i2c.h> 24#include <linux/i2c-algo-bit.h> 25#include <linux/kdev_t.h> 26#include <linux/slab.h> 27 28#include <media/v4l2-device.h> 29#include <media/tuner.h> 30#include <media/tveeprom.h> 31#include <media/videobuf-dma-sg.h> 32#include <media/videobuf-dvb.h> 33#include <media/ir-core.h> 34 35#include "btcx-risc.h" 36#include "cx23885-reg.h" 37#include "media/cx2341x.h" 38 39#include <linux/version.h> 40#include <linux/mutex.h> 41 42#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2) 43 44#define UNSET (-1U) 45 46#define CX23885_MAXBOARDS 8 47 48/* Max number of inputs by card */ 49#define MAX_CX23885_INPUT 8 50#define INPUT(nr) (&cx23885_boards[dev->board].input[nr]) 51#define RESOURCE_OVERLAY 1 52#define RESOURCE_VIDEO 2 53#define RESOURCE_VBI 4 54 55#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */ 56 57#define CX23885_BOARD_NOAUTO UNSET 58#define CX23885_BOARD_UNKNOWN 0 59#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1 60#define CX23885_BOARD_HAUPPAUGE_HVR1800 2 61#define CX23885_BOARD_HAUPPAUGE_HVR1250 3 62#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4 63#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5 64#define CX23885_BOARD_HAUPPAUGE_HVR1500 6 65#define CX23885_BOARD_HAUPPAUGE_HVR1200 7 66#define CX23885_BOARD_HAUPPAUGE_HVR1700 8 67#define CX23885_BOARD_HAUPPAUGE_HVR1400 9 68#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10 69#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11 70#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12 71#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13 72#define CX23885_BOARD_TBS_6920 14 73#define CX23885_BOARD_TEVII_S470 15 74#define CX23885_BOARD_DVBWORLD_2005 16 75#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17 76#define CX23885_BOARD_HAUPPAUGE_HVR1270 18 77#define CX23885_BOARD_HAUPPAUGE_HVR1275 19 78#define CX23885_BOARD_HAUPPAUGE_HVR1255 20 79#define CX23885_BOARD_HAUPPAUGE_HVR1210 21 80#define CX23885_BOARD_MYGICA_X8506 22 81#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23 82#define CX23885_BOARD_HAUPPAUGE_HVR1850 24 83#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25 84#define CX23885_BOARD_HAUPPAUGE_HVR1290 26 85#define CX23885_BOARD_MYGICA_X8558PRO 27 86#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28 87 88#define GPIO_0 0x00000001 89#define GPIO_1 0x00000002 90#define GPIO_2 0x00000004 91#define GPIO_3 0x00000008 92#define GPIO_4 0x00000010 93#define GPIO_5 0x00000020 94#define GPIO_6 0x00000040 95#define GPIO_7 0x00000080 96#define GPIO_8 0x00000100 97#define GPIO_9 0x00000200 98#define GPIO_10 0x00000400 99#define GPIO_11 0x00000800 100#define GPIO_12 0x00001000 101#define GPIO_13 0x00002000 102#define GPIO_14 0x00004000 103#define GPIO_15 0x00008000 104 105/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */ 106#define CX23885_NORMS (\ 107 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \ 108 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ 109 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \ 110 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK) 111 112struct cx23885_fmt { 113 char *name; 114 u32 fourcc; /* v4l2 format id */ 115 int depth; 116 int flags; 117 u32 cxformat; 118}; 119 120struct cx23885_ctrl { 121 struct v4l2_queryctrl v; 122 u32 off; 123 u32 reg; 124 u32 mask; 125 u32 shift; 126}; 127 128struct cx23885_tvnorm { 129 char *name; 130 v4l2_std_id id; 131 u32 cxiformat; 132 u32 cxoformat; 133}; 134 135struct cx23885_fh { 136 struct cx23885_dev *dev; 137 enum v4l2_buf_type type; 138 int radio; 139 u32 resources; 140 141 /* video overlay */ 142 struct v4l2_window win; 143 struct v4l2_clip *clips; 144 unsigned int nclips; 145 146 /* video capture */ 147 struct cx23885_fmt *fmt; 148 unsigned int width, height; 149 150 /* vbi capture */ 151 struct videobuf_queue vidq; 152 struct videobuf_queue vbiq; 153 154 /* MPEG Encoder specifics ONLY */ 155 struct videobuf_queue mpegq; 156 atomic_t v4l_reading; 157}; 158 159enum cx23885_itype { 160 CX23885_VMUX_COMPOSITE1 = 1, 161 CX23885_VMUX_COMPOSITE2, 162 CX23885_VMUX_COMPOSITE3, 163 CX23885_VMUX_COMPOSITE4, 164 CX23885_VMUX_SVIDEO, 165 CX23885_VMUX_COMPONENT, 166 CX23885_VMUX_TELEVISION, 167 CX23885_VMUX_CABLE, 168 CX23885_VMUX_DVB, 169 CX23885_VMUX_DEBUG, 170 CX23885_RADIO, 171}; 172 173enum cx23885_src_sel_type { 174 CX23885_SRC_SEL_EXT_656_VIDEO = 0, 175 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO 176}; 177 178/* buffer for one video frame */ 179struct cx23885_buffer { 180 /* common v4l buffer stuff -- must be first */ 181 struct videobuf_buffer vb; 182 183 /* cx23885 specific */ 184 unsigned int bpl; 185 struct btcx_riscmem risc; 186 struct cx23885_fmt *fmt; 187 u32 count; 188}; 189 190struct cx23885_input { 191 enum cx23885_itype type; 192 unsigned int vmux; 193 u32 gpio0, gpio1, gpio2, gpio3; 194}; 195 196typedef enum { 197 CX23885_MPEG_UNDEFINED = 0, 198 CX23885_MPEG_DVB, 199 CX23885_ANALOG_VIDEO, 200 CX23885_MPEG_ENCODER, 201} port_t; 202 203struct cx23885_board { 204 char *name; 205 port_t porta, portb, portc; 206 unsigned int tuner_type; 207 unsigned int radio_type; 208 unsigned char tuner_addr; 209 unsigned char radio_addr; 210 211 /* Vendors can and do run the PCIe bridge at different 212 * clock rates, driven physically by crystals on the PCBs. 213 * The core has to accomodate this. This allows the user 214 * to add new boards with new frequencys. The value is 215 * expressed in Hz. 216 * 217 * The core framework will default this value based on 218 * current designs, but it can vary. 219 */ 220 u32 clk_freq; 221 struct cx23885_input input[MAX_CX23885_INPUT]; 222 int cimax; /* for NetUP */ 223}; 224 225struct cx23885_subid { 226 u16 subvendor; 227 u16 subdevice; 228 u32 card; 229}; 230 231struct cx23885_i2c { 232 struct cx23885_dev *dev; 233 234 int nr; 235 236 /* i2c i/o */ 237 struct i2c_adapter i2c_adap; 238 struct i2c_algo_bit_data i2c_algo; 239 struct i2c_client i2c_client; 240 u32 i2c_rc; 241 242 /* 885 registers used for raw addess */ 243 u32 i2c_period; 244 u32 reg_ctrl; 245 u32 reg_stat; 246 u32 reg_addr; 247 u32 reg_rdata; 248 u32 reg_wdata; 249}; 250 251struct cx23885_dmaqueue { 252 struct list_head active; 253 struct list_head queued; 254 struct timer_list timeout; 255 struct btcx_riscmem stopper; 256 u32 count; 257}; 258 259struct cx23885_tsport { 260 struct cx23885_dev *dev; 261 262 int nr; 263 int sram_chno; 264 265 struct videobuf_dvb_frontends frontends; 266 267 /* dma queues */ 268 struct cx23885_dmaqueue mpegq; 269 u32 ts_packet_size; 270 u32 ts_packet_count; 271 272 int width; 273 int height; 274 275 spinlock_t slock; 276 277 /* registers */ 278 u32 reg_gpcnt; 279 u32 reg_gpcnt_ctl; 280 u32 reg_dma_ctl; 281 u32 reg_lngth; 282 u32 reg_hw_sop_ctrl; 283 u32 reg_gen_ctrl; 284 u32 reg_bd_pkt_status; 285 u32 reg_sop_status; 286 u32 reg_fifo_ovfl_stat; 287 u32 reg_vld_misc; 288 u32 reg_ts_clk_en; 289 u32 reg_ts_int_msk; 290 u32 reg_ts_int_stat; 291 u32 reg_src_sel; 292 293 /* Default register vals */ 294 int pci_irqmask; 295 u32 dma_ctl_val; 296 u32 ts_int_msk_val; 297 u32 gen_ctrl_val; 298 u32 ts_clk_en_val; 299 u32 src_sel_val; 300 u32 vld_misc_val; 301 u32 hw_sop_ctrl_val; 302 303 /* Allow a single tsport to have multiple frontends */ 304 u32 num_frontends; 305 void *port_priv; 306}; 307 308struct cx23885_kernel_ir { 309 struct cx23885_dev *cx; 310 char *name; 311 char *phys; 312 313 struct input_dev *inp_dev; 314 struct ir_dev_props props; 315}; 316 317struct cx23885_dev { 318 atomic_t refcount; 319 struct v4l2_device v4l2_dev; 320 321 /* pci stuff */ 322 struct pci_dev *pci; 323 unsigned char pci_rev, pci_lat; 324 int pci_bus, pci_slot; 325 u32 __iomem *lmmio; 326 u8 __iomem *bmmio; 327 int pci_irqmask; 328 spinlock_t pci_irqmask_lock; /* protects mask reg too */ 329 int hwrevision; 330 331 /* This valud is board specific and is used to configure the 332 * AV core so we see nice clean and stable video and audio. */ 333 u32 clk_freq; 334 335 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ 336 struct cx23885_i2c i2c_bus[3]; 337 338 int nr; 339 struct mutex lock; 340 struct mutex gpio_lock; 341 342 /* board details */ 343 unsigned int board; 344 char name[32]; 345 346 struct cx23885_tsport ts1, ts2; 347 348 /* sram configuration */ 349 struct sram_channel *sram_channels; 350 351 enum { 352 CX23885_BRIDGE_UNDEFINED = 0, 353 CX23885_BRIDGE_885 = 885, 354 CX23885_BRIDGE_887 = 887, 355 CX23885_BRIDGE_888 = 888, 356 } bridge; 357 358 /* Analog video */ 359 u32 resources; 360 unsigned int input; 361 u32 tvaudio; 362 v4l2_std_id tvnorm; 363 unsigned int tuner_type; 364 unsigned char tuner_addr; 365 unsigned int radio_type; 366 unsigned char radio_addr; 367 unsigned int has_radio; 368 struct v4l2_subdev *sd_cx25840; 369 struct work_struct cx25840_work; 370 371 /* Infrared */ 372 struct v4l2_subdev *sd_ir; 373 struct work_struct ir_rx_work; 374 unsigned long ir_rx_notifications; 375 struct work_struct ir_tx_work; 376 unsigned long ir_tx_notifications; 377 378 struct cx23885_kernel_ir *kernel_ir; 379 atomic_t ir_input_stopping; 380 381 /* V4l */ 382 u32 freq; 383 struct video_device *video_dev; 384 struct video_device *vbi_dev; 385 struct video_device *radio_dev; 386 387 struct cx23885_dmaqueue vidq; 388 struct cx23885_dmaqueue vbiq; 389 spinlock_t slock; 390 391 /* MPEG Encoder ONLY settings */ 392 u32 cx23417_mailbox; 393 struct cx2341x_mpeg_params mpeg_params; 394 struct video_device *v4l_device; 395 atomic_t v4l_reader_count; 396 struct cx23885_tvnorm encodernorm; 397 398}; 399 400static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev) 401{ 402 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev); 403} 404 405#define call_all(dev, o, f, args...) \ 406 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args) 407 408#define CX23885_HW_888_IR (1 << 0) 409#define CX23885_HW_AV_CORE (1 << 1) 410 411#define call_hw(dev, grpid, o, f, args...) \ 412 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args) 413 414extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw); 415 416#define SRAM_CH01 0 /* Video A */ 417#define SRAM_CH02 1 /* VBI A */ 418#define SRAM_CH03 2 /* Video B */ 419#define SRAM_CH04 3 /* Transport via B */ 420#define SRAM_CH05 4 /* VBI B */ 421#define SRAM_CH06 5 /* Video C */ 422#define SRAM_CH07 6 /* Transport via C */ 423#define SRAM_CH08 7 /* Audio Internal A */ 424#define SRAM_CH09 8 /* Audio Internal B */ 425#define SRAM_CH10 9 /* Audio External */ 426#define SRAM_CH11 10 /* COMB_3D_N */ 427#define SRAM_CH12 11 /* Comb 3D N1 */ 428#define SRAM_CH13 12 /* Comb 3D N2 */ 429#define SRAM_CH14 13 /* MOE Vid */ 430#define SRAM_CH15 14 /* MOE RSLT */ 431 432struct sram_channel { 433 char *name; 434 u32 cmds_start; 435 u32 ctrl_start; 436 u32 cdt; 437 u32 fifo_start; 438 u32 fifo_size; 439 u32 ptr1_reg; 440 u32 ptr2_reg; 441 u32 cnt1_reg; 442 u32 cnt2_reg; 443 u32 jumponly; 444}; 445 446/* ----------------------------------------------------------- */ 447 448#define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) 449#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) 450 451#define cx_andor(reg, mask, value) \ 452 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ 453 ((value) & (mask)), dev->lmmio+((reg)>>2)) 454 455#define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) 456#define cx_clear(reg, bit) cx_andor((reg), (bit), 0) 457 458/* ----------------------------------------------------------- */ 459/* cx23885-core.c */ 460 461extern int cx23885_sram_channel_setup(struct cx23885_dev *dev, 462 struct sram_channel *ch, 463 unsigned int bpl, u32 risc); 464 465extern void cx23885_sram_channel_dump(struct cx23885_dev *dev, 466 struct sram_channel *ch); 467 468extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, 469 u32 reg, u32 mask, u32 value); 470 471extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, 472 struct scatterlist *sglist, 473 unsigned int top_offset, unsigned int bottom_offset, 474 unsigned int bpl, unsigned int padding, unsigned int lines); 475 476void cx23885_cancel_buffers(struct cx23885_tsport *port); 477 478extern int cx23885_restart_queue(struct cx23885_tsport *port, 479 struct cx23885_dmaqueue *q); 480 481extern void cx23885_wakeup(struct cx23885_tsport *port, 482 struct cx23885_dmaqueue *q, u32 count); 483 484extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask); 485extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask); 486extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask); 487extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, 488 int asoutput); 489 490extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask); 491extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask); 492extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask); 493extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask); 494 495/* ----------------------------------------------------------- */ 496/* cx23885-cards.c */ 497extern struct cx23885_board cx23885_boards[]; 498extern const unsigned int cx23885_bcount; 499 500extern struct cx23885_subid cx23885_subids[]; 501extern const unsigned int cx23885_idcount; 502 503extern int cx23885_tuner_callback(void *priv, int component, 504 int command, int arg); 505extern void cx23885_card_list(struct cx23885_dev *dev); 506extern int cx23885_ir_init(struct cx23885_dev *dev); 507extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev); 508extern void cx23885_ir_fini(struct cx23885_dev *dev); 509extern void cx23885_gpio_setup(struct cx23885_dev *dev); 510extern void cx23885_card_setup(struct cx23885_dev *dev); 511extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev); 512 513extern int cx23885_dvb_register(struct cx23885_tsport *port); 514extern int cx23885_dvb_unregister(struct cx23885_tsport *port); 515 516extern int cx23885_buf_prepare(struct videobuf_queue *q, 517 struct cx23885_tsport *port, 518 struct cx23885_buffer *buf, 519 enum v4l2_field field); 520extern void cx23885_buf_queue(struct cx23885_tsport *port, 521 struct cx23885_buffer *buf); 522extern void cx23885_free_buffer(struct videobuf_queue *q, 523 struct cx23885_buffer *buf); 524 525/* ----------------------------------------------------------- */ 526/* cx23885-video.c */ 527/* Video */ 528extern int cx23885_video_register(struct cx23885_dev *dev); 529extern void cx23885_video_unregister(struct cx23885_dev *dev); 530extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status); 531 532/* ----------------------------------------------------------- */ 533/* cx23885-vbi.c */ 534extern int cx23885_vbi_fmt(struct file *file, void *priv, 535 struct v4l2_format *f); 536extern void cx23885_vbi_timeout(unsigned long data); 537extern struct videobuf_queue_ops cx23885_vbi_qops; 538 539/* cx23885-i2c.c */ 540extern int cx23885_i2c_register(struct cx23885_i2c *bus); 541extern int cx23885_i2c_unregister(struct cx23885_i2c *bus); 542extern void cx23885_av_clk(struct cx23885_dev *dev, int enable); 543 544/* ----------------------------------------------------------- */ 545/* cx23885-417.c */ 546extern int cx23885_417_register(struct cx23885_dev *dev); 547extern void cx23885_417_unregister(struct cx23885_dev *dev); 548extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status); 549extern void cx23885_417_check_encoder(struct cx23885_dev *dev); 550extern void cx23885_mc417_init(struct cx23885_dev *dev); 551extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value); 552extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value); 553extern int mc417_register_read(struct cx23885_dev *dev, 554 u16 address, u32 *value); 555extern int mc417_register_write(struct cx23885_dev *dev, 556 u16 address, u32 value); 557extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask); 558extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask); 559extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); 560 561 562/* ----------------------------------------------------------- */ 563/* tv norms */ 564 565static inline unsigned int norm_maxw(v4l2_std_id norm) 566{ 567 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768; 568} 569 570static inline unsigned int norm_maxh(v4l2_std_id norm) 571{ 572 return (norm & V4L2_STD_625_50) ? 576 : 480; 573} 574 575static inline unsigned int norm_swidth(v4l2_std_id norm) 576{ 577 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922; 578} 579