Searched refs:__REG (Results 1 - 25 of 30) sorted by relevance

12

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/
H A Dregs-intc.h10 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
11 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
12 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
13 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
16 #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
18 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
19 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
20 #define ICLR2 __REG(
[all...]
H A Dpxa27x-udc.h8 #define UDCCR __REG(0x40600000) /* UDC Control Register */
32 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
47 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
56 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
84 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
103 #define UDCCSR0 __REG(
[all...]
H A Dregs-ost.h10 #define OSMR0 __REG(0x40A00000) /* */
11 #define OSMR1 __REG(0x40A00004) /* */
12 #define OSMR2 __REG(0x40A00008) /* */
13 #define OSMR3 __REG(0x40A0000C) /* */
14 #define OSMR4 __REG(0x40A00080) /* */
15 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
16 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
17 #define OMCR4 __REG(0x40A000C0) /* */
18 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
19 #define OWER __REG(
[all...]
H A Dregs-uart.h10 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19 #define FFSPR __REG(
[all...]
H A Dregs-ac97.h10 #define POCR __REG(0x40500000) /* PCM Out Control Register */
14 #define PICR __REG(0x40500004) /* PCM In Control Register */
18 #define MCCR __REG(0x40500008) /* Mic In Control Register */
22 #define GCR __REG(0x4050000C) /* Global Control Register */
38 #define POSR __REG(0x40500010) /* PCM Out Status Register */
42 #define PISR __REG(0x40500014) /* PCM In Status Register */
47 #define MCSR __REG(0x40500018) /* Mic In Status Register */
52 #define GSR __REG(0x4050001C) /* Global Status Register */
71 #define CAR __REG(0x40500020) /* CODEC Access Register */
74 #define PCDR __REG(
[all...]
H A Dregs-rtc.h10 #define RCNR __REG(0x40900000) /* RTC Count Register */
11 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
12 #define RTSR __REG(0x40900008) /* RTC Status Register */
13 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
14 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
H A Dpxa25x-udc.h8 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
12 #define UDCCR __REG(0x40600000) /* UDC Control Register */
22 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
33 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
46 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47 #define UDCCS7 __REG(
[all...]
H A Dpxa2xx-regs.h34 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
35 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
36 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
37 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
38 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
39 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
40 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
41 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
42 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
43 #define MCMEM0 __REG(
[all...]
H A Dpxa3xx-regs.h30 #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
38 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
39 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
40 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
41 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
42 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
43 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
44 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
45 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
46 #define PVCR __REG(
[all...]
H A Dpxa27x.h8 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-aaec2000/include/mach/
H A Daaec2000.h31 #define IRQ_BASE __REG(0x80000500)
32 #define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
33 #define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
34 #define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
35 #define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
38 #define UART1_BASE __REG(0x80000600)
39 #define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
40 #define UART1_LCR __REG(0x80000604) /* Link Control Register */
41 #define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
42 #define UART1_CR __REG(
[all...]
H A Dhardware.h37 #define __REG(x) (*((volatile u32 *)io_p2v(x))) macro
42 #define __REG(x) io_p2v(x) macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-lh7a40x/include/mach/
H A Dregisters.h58 #define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
59 #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
60 #define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
61 #define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
87 #define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
88 #define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
89 #define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
90 #define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
95 #define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
96 #define VIC1_FIQSTATUS __REG(VIC1_PHY
[all...]
H A Ddma.h26 #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27 #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
55 #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56 #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57 #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58 #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59 #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60 #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61 #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62 #define DMAC_P_CURRENT0(c) __REG(DMAC_PHY
[all...]
H A Dhardware.h23 # define __REG(x) io_p2v(x) macro
29 * This __REG() version gives the same results as the one above, except
37 # define __REG(x) __REGP(io_p2v(x)) macro
47 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
48 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-ns9xxx/include/mach/
H A Dregs-mem.h19 #define MEM_CTRL __REG(0xa0700000)
22 #define MEM_STAT __REG(0xa0700004)
25 #define MEM_CONF __REG(0xa0700008)
28 #define MEM_DMCTRL __REG(0xa0700020)
31 #define MEM_DMRT __REG(0xa0700024)
34 #define MEM_DMRC __REG(0xa0700028)
37 #define MEM_DMPCP __REG(0xa0700030)
40 #define MEM_DMAPCP __REG(0xa0700034)
43 #define MEM_DMSRET __REG(0xa0700038)
46 #define MEM_DMLDOAT __REG(
[all...]
H A Dregs-sys-common.h23 #define SYS_ISRADDR __REG(0xa0900164)
26 #define SYS_ISA __REG(0xa0900168)
29 #define SYS_ISR __REG(0xa090016c)
H A Dregs-board-a9m9750dev.h21 #define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22 #define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
H A Duncompress.h16 #define __REG(x) ((void __iomem __force *)(x)) macro
68 #define MSCS __REG(0xA0900184)
70 #define NS9360_UARTA __REG(0x90200040)
71 #define NS9360_UARTB __REG(0x90200000)
72 #define NS9360_UARTC __REG(0x90300000)
73 #define NS9360_UARTD __REG(0x90300040)
78 #define A9M9750DEV_UARTA __REG(0x40000000)
80 #define NS921XSYS_CLOCK __REG(0xa090017c)
81 #define NS921X_UARTA __REG(0x90010000)
82 #define NS921X_UARTB __REG(
[all...]
H A Dregs-bbu.h37 #define BBU_GCTRL1 __REG(0x90600030)
38 #define BBU_GCTRL2 __REG(0x90600034)
39 #define BBU_GCTRL3 __REG(0x90600120)
41 #define BBU_GSTAT1 __REG(0x90600040)
42 #define BBU_GSTAT2 __REG(0x90600044)
43 #define BBU_GSTAT3 __REG(0x90600130)
H A Dregs-sys-ns9360.h19 #define SYS_AHBAGENCONF __REG(0xa0900000)
31 #define SYS_TIS __REG(0xa0900170)
34 #define SYS_PLL __REG(0xa0900188)
127 #define SYS_GENID __REG(0xa0900210)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(
[all...]
H A Dhardware.h59 # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) macro
68 # define __REG(x) io_p2v(x) macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-dove/include/mach/
H A Dhardware.h22 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-lh7a40x/
H A Dclcd.c31 #define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
32 #define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
33 #define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
34 #define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
36 #define ALI_SETUP __REG(ALI_PHYS + 0x00)
37 #define ALI_CONTROL __REG(ALI_PHYS + 0x04)
38 #define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
39 #define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)

Completed in 276 milliseconds

12