Lines Matching refs:__REG
110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
120 #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
266 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
267 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
268 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
269 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
270 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
271 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
272 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
273 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
423 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
424 #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
425 #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
426 #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
427 #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
428 #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
429 #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
430 #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
532 #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
533 #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
534 #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
535 #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
536 #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
537 #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
614 #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
615 #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
616 #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
617 #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
618 #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
619 #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
737 #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
738 #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
739 #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
740 #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
818 #define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
819 #define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
820 #define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
821 #define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
822 #define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
823 #define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
824 #define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
825 #define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
861 #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */
862 #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */
863 #define RTTR __REG(0x90010008) /* RTC Trim Reg. */
864 #define RTSR __REG(0x90010010) /* RTC Status Reg. */
902 #define PMCR __REG(0x90020000) /* PM Control Reg. */
903 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
904 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
905 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
906 #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
907 #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
908 #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
909 #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
1043 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
1044 #define RCSR __REG(0x90030004) /* RC Status Reg. */
1061 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
1123 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
1124 #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
1125 #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
1126 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
1127 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1128 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1129 #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
1130 #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
1228 #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
1229 #define ICMR __REG(0x90050004) /* IC Mask Reg. */
1230 #define ICLR __REG(0x90050008) /* IC Level Reg. */
1231 #define ICCR __REG(0x9005000C) /* IC Control Reg. */
1232 #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
1233 #define ICPR __REG(0x90050020) /* IC Pending Reg. */
1301 #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
1302 #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
1303 #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
1304 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1305 #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
1386 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
1387 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
1388 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1389 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
1461 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
1462 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
1463 #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
1531 #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
1559 #define MDREFR __REG(0xA000001C)
1661 #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
1662 #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
1663 #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
1664 #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
1665 #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
1666 #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
1667 #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
1668 #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
1891 #define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
1892 #define LCSR __REG(0xB0100004) /* LCD Status Reg. */
1893 #define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
1894 #define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
1895 #define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
1896 #define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
1897 #define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
1898 #define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
1899 #define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */