Lines Matching refs:__REG
31 #define IRQ_BASE __REG(0x80000500)
32 #define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
33 #define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
34 #define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
35 #define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
38 #define UART1_BASE __REG(0x80000600)
39 #define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
40 #define UART1_LCR __REG(0x80000604) /* Link Control Register */
41 #define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
42 #define UART1_CR __REG(0x8000060c) /* Control Register */
43 #define UART1_SR __REG(0x80000610) /* Status Register */
44 #define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
45 #define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
46 #define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
49 #define UART2_BASE __REG(0x80000700)
50 #define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
51 #define UART2_LCR __REG(0x80000704) /* Link Control Register */
52 #define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
53 #define UART2_CR __REG(0x8000070c) /* Control Register */
54 #define UART2_SR __REG(0x80000710) /* Status Register */
55 #define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
56 #define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
57 #define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
60 #define UART3_BASE __REG(0x80000800)
61 #define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
62 #define UART3_LCR __REG(0x80000804) /* Link Control Register */
63 #define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
64 #define UART3_CR __REG(0x8000080c) /* Control Register */
65 #define UART3_SR __REG(0x80000810) /* Status Register */
66 #define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
67 #define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
68 #define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
122 #define TIMER1_BASE __REG(0x80000c00)
123 #define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
124 #define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
125 #define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
126 #define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
129 #define TIMER2_BASE __REG(0x80000d00)
130 #define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
131 #define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
132 #define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
133 #define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
136 #define TIMER3_BASE __REG(0x80000e00)
137 #define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
138 #define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
139 #define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
140 #define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
150 #define POWER_BASE __REG(0x80000400)
151 #define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
152 #define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
153 #define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
154 #define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
155 #define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
156 #define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
157 #define POWER_TEOI __REG(0x80000418) /* Tick EoI */
158 #define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
159 #define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
164 #define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
165 #define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
166 #define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
167 #define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
168 #define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
169 #define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
170 #define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
171 #define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
172 #define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
173 #define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
174 #define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
175 #define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
176 #define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
177 #define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
178 #define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
179 #define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
180 #define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
181 #define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
182 #define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
183 #define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
184 #define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
185 #define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
186 #define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
187 #define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
188 #define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
189 #define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
190 #define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
191 #define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
192 #define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
193 #define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
194 #define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
195 #define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
196 #define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
197 #define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)