Searched refs:TSB (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sparc/include/asm/
H A Dtsb.h4 /* The sparc64 TSB is similar to the powerpc hashtables. It's a
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
41 * We need to carefully choose a lock bits for the TSB entry. We
54 * those if possible so we don't need to hard-lock the TSB mapping
58 * The kernel TSB is locked into the TLB by virtue of being in the
76 #define TSB_LOAD_QUAD(TSB, REG) \
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sparc/kernel/
H A Ddtlb_miss.S1 /* DTLB ** ICACHE line 1: Context 0 check and TSB load */
2 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
8 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
11 /* DTLB ** ICACHE line 2: TSB compare and TLB load */
H A Ditlb_miss.S1 /* ITLB ** ICACHE line 1: Context 0 check and TSB load */
2 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
8 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
11 /* ITLB ** ICACHE line 2: TSB compare and TLB load */
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/amule/libcryptoxx-5.6.0/
H A Dsquare.cpp71 #define TSB(x) (((x) >> 8) & 0xffU) /* third in significance */ macro
86 temp[2] = T0[TSB (text[0])] \
87 ^ T1[TSB (text[1])] \
88 ^ T2[TSB (text[2])] \
89 ^ T3[TSB (text[3])] \
110 text[2] = ((word32) (S[TSB (temp[0])]) << 24) \
111 ^ ((word32) (S[TSB (temp[1])]) << 16) \
112 ^ ((word32) (S[TSB (temp[2])]) << 8) \
113 ^ (word32) (S[TSB (temp[3])]) \

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