Lines Matching refs:TSB
4 /* The sparc64 TSB is similar to the powerpc hashtables. It's a
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
41 * We need to carefully choose a lock bits for the TSB entry. We
54 * those if possible so we don't need to hard-lock the TSB mapping
58 * The kernel TSB is locked into the TLB by virtue of being in the
76 #define TSB_LOAD_QUAD(TSB, REG) \
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \
85 661: lduwa [TSB] ASI_N, REG; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 #define TSB_LOAD_TAG(TSB, REG) \
92 661: ldxa [TSB] ASI_N, REG; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \
120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
130 #define TSB_WRITE(TSB, TTE, TAG) \
131 add TSB, 0x8, TSB; \
132 TSB_STORE(TSB, TTE); \
133 sub TSB, 0x8, TSB; \
134 TSB_STORE(TSB, TAG);
136 #define KTSB_LOAD_QUAD(TSB, REG) \
137 ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
142 #define KTSB_LOCK_TAG(TSB, REG1, REG2) \
143 99: lduwa [TSB] ASI_N, REG1; \
148 casa [TSB] ASI_N, REG1, REG2;\
153 #define KTSB_WRITE(TSB, TTE, TAG) \
154 add TSB, 0x8, TSB; \
155 stxa TTE, [TSB] ASI_N; \
156 sub TSB, 0x8, TSB; \
157 stxa TAG, [TSB] ASI_N;
233 /* We use a 32K TSB for the whole kernel, this allows to
242 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
243 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries