Searched refs:SPORT0_RCLKDIV (Results 1 - 14 of 14) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h559 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
560 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
H A DdefBF532.h130 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF547.h77 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
78 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
H A DdefBF547.h51 #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h277 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
278 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
H A DdefBF51x_base.h169 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h294 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
295 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
H A DdefBF52x_base.h166 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h147 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro
H A DcdefBF534.h258 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
259 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h252 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro
H A DcdefBF561.h412 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
413 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h240 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
241 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
H A DdefBF539.h142 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ macro

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