1/* 2 * Copyright 2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later 5 */ 6 7#ifndef _CDEF_BF52X_H 8#define _CDEF_BF52X_H 9 10#include <asm/blackfin.h> 11 12#include "defBF51x_base.h" 13 14/* Include core specific register pointer definitions */ 15#include <asm/cdef_LPBlackfin.h> 16 17/* ==== begin from cdefBF534.h ==== */ 18 19/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 20#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 21#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 22#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 23#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 24#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 25#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 26#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 27#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 28#define bfin_read_CHIPID() bfin_read32(CHIPID) 29#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) 30 31 32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 33#define bfin_read_SWRST() bfin_read16(SWRST) 34#define bfin_write_SWRST(val) bfin_write16(SWRST, val) 35#define bfin_read_SYSCR() bfin_read16(SYSCR) 36#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) 37 38#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) 39#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) 40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) 41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) 42#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) 43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) 44 45#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 46#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) 47#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) 48#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) 49#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) 50#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) 51#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) 52#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) 53 54#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 55#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 56#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) 57#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) 58 59#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 60#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 61#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) 62#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) 63 64/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ 65 66#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) 67#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) 68#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) 69#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) 70#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) 71#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) 72#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) 73#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) 74#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) 75#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) 76#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) 77#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) 78#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) 79#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) 80 81/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 82#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) 83#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) 84#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) 85#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) 86#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) 87#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) 88 89 90/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 91#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) 92#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) 93#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) 94#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) 95#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) 96#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) 97#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) 98#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) 99#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) 100#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) 101#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) 102#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) 103#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) 104#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) 105 106 107/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 108#define bfin_read_UART0_THR() bfin_read16(UART0_THR) 109#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) 110#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) 111#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) 112#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) 113#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) 114#define bfin_read_UART0_IER() bfin_read16(UART0_IER) 115#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) 116#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) 117#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) 118#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) 119#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) 120#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) 121#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) 122#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) 123#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) 124#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) 125#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) 126#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) 127#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) 128#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) 129#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) 130#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) 131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) 132 133 134/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ 135#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 136#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) 137#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) 138#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) 139#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) 140#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) 141#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) 142#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) 143 144#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) 145#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) 146#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) 147#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) 148#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) 149#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) 150#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) 151#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) 152 153#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) 154#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) 155#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) 156#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) 157#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) 158#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) 159#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) 160#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) 161 162#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) 163#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) 164#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) 165#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) 166#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) 167#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) 168#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) 169#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) 170 171#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) 172#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) 173#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) 174#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) 175#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) 176#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) 177#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) 178#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) 179 180#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) 181#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) 182#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) 183#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) 184#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) 185#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) 186#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) 187#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) 188 189#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) 190#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) 191#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) 192#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) 193#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) 194#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) 195#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) 196#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) 197 198#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) 199#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) 200#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) 201#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) 202#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) 203#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) 204#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) 205#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) 206 207#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 208#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) 209#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) 210#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) 211#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) 212#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) 213 214 215/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ 216#define bfin_read_PORTFIO() bfin_read16(PORTFIO) 217#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) 218#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) 219#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) 220#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) 221#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) 222#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) 223#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) 224#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) 225#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) 226#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) 227#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) 228#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) 229#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) 230#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) 231#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) 232#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) 233#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) 234#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) 235#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) 236#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) 237#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) 238#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) 239#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) 240#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) 241#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) 242#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) 243#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) 244#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) 245#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) 246#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) 247#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) 248#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) 249#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) 250 251 252/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 253#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) 254#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) 255#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) 256#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) 257#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) 258#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) 259#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) 260#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) 261#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) 262#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 263#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 264#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 265#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) 266#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) 267#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) 268#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) 269#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) 270#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) 271#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) 272#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) 273#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 274#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 275#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 276#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) 277#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) 278#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) 279#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) 280#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) 281#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) 282#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) 283#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) 284#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) 285#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) 286#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) 287#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) 288#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) 289#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) 290#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) 291#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) 292#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) 293#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) 294#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) 295#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) 296#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) 297#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) 298#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) 299#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) 300#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) 301#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) 302#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) 303#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) 304#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) 305 306 307/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 308#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) 309#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) 310#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) 311#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) 312#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) 313#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) 314#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) 315#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) 316#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) 317#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 318#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 319#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 320#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) 321#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) 322#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) 323#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) 324#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) 325#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) 326#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) 327#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) 328#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 329#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 330#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 331#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) 332#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) 333#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) 334#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) 335#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) 336#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) 337#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) 338#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) 339#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) 340#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) 341#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) 342#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) 343#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) 344#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) 345#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) 346#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) 347#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) 348#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) 349#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) 350#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) 351#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) 352#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) 353#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) 354#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) 355#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) 356#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) 357#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) 358#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) 359#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) 360 361 362/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 363#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) 364#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) 365#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) 366#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) 367#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) 368#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) 369#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) 370#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) 371#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 372#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) 373#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) 374#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) 375#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) 376#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) 377 378 379/* DMA Traffic Control Registers */ 380#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 381#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) 382#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 383#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) 384 385/* Alternate deprecated register names (below) provided for backwards code compatibility */ 386#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) 387#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) 388#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) 389#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) 390 391/* DMA Controller */ 392#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 393#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) 394#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) 395#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) 396#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) 397#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) 398#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) 399#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) 400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) 401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) 402#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) 403#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) 404#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) 405#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) 406#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) 407#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) 408#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) 409#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) 410#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) 411#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) 412#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) 413#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) 414#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) 415#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) 416#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) 417#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) 418 419#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) 420#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) 421#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) 422#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) 423#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) 424#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) 425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) 426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) 427#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) 428#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) 429#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) 430#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) 431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) 432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) 433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) 434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) 435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) 436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) 437#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) 438#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) 439#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) 440#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) 441#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) 442#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) 443#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) 444#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) 445 446#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) 447#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) 448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) 449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) 450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) 451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) 452#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) 453#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) 454#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) 455#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) 456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) 457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) 458#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) 459#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) 460#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) 461#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) 462#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) 463#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) 464#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) 465#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) 466#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) 467#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) 468#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) 469#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) 470#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) 471#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) 472 473#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) 474#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) 475#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) 476#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) 477#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) 478#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) 479#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) 480#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) 481#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) 482#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) 483#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) 484#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) 485#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) 486#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) 487#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) 488#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) 489#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) 490#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) 491#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) 492#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) 493#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) 494#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) 495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) 496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) 497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) 498#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) 499 500#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) 501#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) 502#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) 503#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) 504#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) 505#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) 506#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) 507#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) 508#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) 509#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) 510#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) 511#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) 512#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) 513#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) 514#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) 515#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) 516#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) 517#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) 518#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) 519#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) 520#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) 521#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) 522#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) 523#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) 524#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) 525#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) 526 527#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) 528#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) 529#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) 530#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) 531#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) 532#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) 533#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) 534#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) 535#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 536#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) 537#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) 538#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) 539#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) 540#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) 541#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) 542#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) 543#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) 544#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) 545#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) 546#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) 547#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) 548#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) 549#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) 550#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) 551#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) 552#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) 553 554#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) 555#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) 556#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) 557#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) 558#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) 559#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) 560#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) 561#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) 562#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) 563#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) 564#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) 565#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) 566#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) 567#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) 568#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) 569#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) 570#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) 571#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) 572#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) 573#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) 574#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) 575#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) 576#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) 577#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) 578#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) 579#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) 580 581#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) 582#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) 583#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) 584#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) 585#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) 586#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) 587#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) 588#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) 589#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) 590#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) 591#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) 592#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) 593#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) 594#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) 595#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) 596#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) 597#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) 598#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) 599#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) 600#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) 601#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) 602#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) 603#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) 604#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) 605#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) 606#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) 607 608#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) 609#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) 610#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) 611#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) 612#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) 613#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) 614#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) 615#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) 616#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) 617#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) 618#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) 619#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) 620#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) 621#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) 622#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) 623#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) 624#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) 625#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) 626#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) 627#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) 628#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) 629#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) 630#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) 631#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) 632#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) 633#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) 634 635#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) 636#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) 637#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) 638#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) 639#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) 640#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) 641#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) 642#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) 643#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) 644#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) 645#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) 646#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) 647#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) 648#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) 649#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) 650#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) 651#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) 652#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) 653#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) 654#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) 655#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) 656#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) 657#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) 658#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) 659#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) 660#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) 661 662#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) 663#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) 664#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) 665#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) 666#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) 667#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) 668#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) 669#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) 670#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) 671#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) 672#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) 673#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) 674#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) 675#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) 676#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) 677#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) 678#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) 679#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) 680#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) 681#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) 682#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) 683#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) 684#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) 685#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) 686#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) 687#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) 688 689#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) 690#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) 691#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) 692#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) 693#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) 694#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) 695#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) 696#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) 697#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) 698#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) 699#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) 700#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) 701#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) 702#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) 703#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) 704#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) 705#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) 706#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) 707#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) 708#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) 709#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) 710#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) 711#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) 712#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) 713#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) 714#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) 715 716#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 717#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) 718#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 719#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) 720#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 721#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) 722#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) 723#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) 724#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) 725#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) 726#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) 727#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) 728#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) 729#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) 730#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) 731#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) 732#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) 733#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) 734#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) 735#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) 736#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) 737#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) 738#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) 739#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) 740#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) 741#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) 742 743#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) 744#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) 745#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) 746#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) 747#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) 748#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) 749#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) 750#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) 751#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) 752#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) 753#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) 754#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) 755#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) 756#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) 757#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) 758#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) 759#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) 760#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) 761#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) 762#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) 763#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) 764#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) 765#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) 766#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) 767#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) 768#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) 769 770#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) 771#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) 772#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) 773#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) 774#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) 775#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) 776#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 777#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) 778#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) 779#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) 780#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) 781#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) 782#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 783#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) 784#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 785#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) 786#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 787#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) 788#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) 789#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) 790#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) 791#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) 792#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) 793#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) 794#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) 795#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) 796 797#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) 798#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) 799#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) 800#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) 801#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) 802#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) 803#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 804#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) 805#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) 806#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) 807#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) 808#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) 809#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 810#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) 811#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 812#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) 813#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 814#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) 815#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) 816#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) 817#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) 818#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) 819#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) 820#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) 821#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) 822#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) 823 824 825/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ 826#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) 827#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 828#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 829#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) 830#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) 831#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) 832#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) 833#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) 834#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) 835#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 836#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) 837 838 839/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 840 841/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 842#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 843#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) 844#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) 845#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) 846#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) 847#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) 848#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) 849#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) 850#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) 851#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) 852#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) 853#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) 854#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) 855#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) 856#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) 857#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) 858#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) 859#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) 860#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) 861#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) 862#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) 863#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) 864#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) 865#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) 866#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) 867#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) 868#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) 869#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) 870#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) 871#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) 872#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) 873#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) 874#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) 875#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) 876 877 878/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ 879#define bfin_read_PORTHIO() bfin_read16(PORTHIO) 880#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) 881#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) 882#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) 883#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) 884#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) 885#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) 886#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) 887#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) 888#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) 889#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) 890#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) 891#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) 892#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) 893#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) 894#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) 895#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) 896#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) 897#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) 898#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) 899#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) 900#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) 901#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) 902#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) 903#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) 904#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) 905#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) 906#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) 907#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) 908#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) 909#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) 910#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) 911#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) 912#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) 913 914 915/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 916#define bfin_read_UART1_THR() bfin_read16(UART1_THR) 917#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) 918#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) 919#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) 920#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) 921#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) 922#define bfin_read_UART1_IER() bfin_read16(UART1_IER) 923#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) 924#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) 925#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) 926#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) 927#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) 928#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) 929#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) 930#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) 931#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) 932#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) 933#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) 934#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) 935#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) 936#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) 937#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) 938#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) 939#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) 940 941/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ 942 943/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ 944#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) 945#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) 946#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) 947#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) 948#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) 949#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) 950#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) 951#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) 952 953 954/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ 955#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) 956#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) 957#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) 958#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) 959#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) 960#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) 961#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) 962#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) 963#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) 964#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) 965#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) 966#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) 967#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) 968#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) 969 970#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) 971#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) 972#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) 973#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) 974#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) 975#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) 976#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) 977#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) 978#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) 979#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) 980#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) 981#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) 982#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 983#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) 984 985/* ==== end from cdefBF534.h ==== */ 986 987/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ 988 989#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) 990#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) 991#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) 992#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) 993#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) 994#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) 995 996#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) 997#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) 998#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) 999#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) 1000#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) 1001#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) 1002#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) 1003#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) 1004#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) 1005#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) 1006#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) 1007#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) 1008#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) 1009#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) 1010#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) 1011#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) 1012#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) 1013#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) 1014#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) 1015#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) 1016#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) 1017#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) 1018#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) 1019#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) 1020 1021/* HOST Port Registers */ 1022 1023#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) 1024#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) 1025#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) 1026#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) 1027#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) 1028#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) 1029 1030/* Counter Registers */ 1031 1032#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) 1033#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) 1034#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) 1035#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) 1036#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) 1037#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) 1038#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) 1039#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) 1040#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) 1041#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) 1042#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) 1043#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) 1044#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) 1045#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) 1046#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1047#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1048 1049/* Security Registers */ 1050 1051#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1052#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) 1053#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) 1054#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) 1055#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1056#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1057 1058/* These need to be last due to the cdef/linux inter-dependencies */ 1059#include <asm/irq.h> 1060 1061/* Writing to PLL_CTL initiates a PLL relock sequence. */ 1062static __inline__ void bfin_write_PLL_CTL(unsigned int val) 1063{ 1064 unsigned long flags, iwr0, iwr1; 1065 1066 if (val == bfin_read_PLL_CTL()) 1067 return; 1068 1069 local_irq_save_hw(flags); 1070 /* Enable the PLL Wakeup bit in SIC IWR */ 1071 iwr0 = bfin_read32(SIC_IWR0); 1072 iwr1 = bfin_read32(SIC_IWR1); 1073 /* Only allow PPL Wakeup) */ 1074 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); 1075 bfin_write32(SIC_IWR1, 0); 1076 1077 bfin_write16(PLL_CTL, val); 1078 SSYNC(); 1079 asm("IDLE;"); 1080 1081 bfin_write32(SIC_IWR0, iwr0); 1082 bfin_write32(SIC_IWR1, iwr1); 1083 local_irq_restore_hw(flags); 1084} 1085 1086/* Writing to VR_CTL initiates a PLL relock sequence. */ 1087static __inline__ void bfin_write_VR_CTL(unsigned int val) 1088{ 1089 unsigned long flags, iwr0, iwr1; 1090 1091 if (val == bfin_read_VR_CTL()) 1092 return; 1093 1094 local_irq_save_hw(flags); 1095 /* Enable the PLL Wakeup bit in SIC IWR */ 1096 iwr0 = bfin_read32(SIC_IWR0); 1097 iwr1 = bfin_read32(SIC_IWR1); 1098 /* Only allow PPL Wakeup) */ 1099 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); 1100 bfin_write32(SIC_IWR1, 0); 1101 1102 bfin_write16(VR_CTL, val); 1103 SSYNC(); 1104 asm("IDLE;"); 1105 1106 bfin_write32(SIC_IWR0, iwr0); 1107 bfin_write32(SIC_IWR1, iwr1); 1108 local_irq_restore_hw(flags); 1109} 1110 1111#endif /* _CDEF_BF52X_H */ 1112