Searched refs:REG_SET_BIT (Results 1 - 13 of 13) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Dar9002_hw.c451 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
506 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
508 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
511 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
536 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
550 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
H A Dbtcoex.c109 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
127 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
H A Dcalib.c162 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
169 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
172 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
211 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
H A Dar9002_calib.c57 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
261 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
743 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
745 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
746 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
750 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
763 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
764 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
765 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
773 REG_SET_BIT(a
[all...]
H A Dar9003_phy.c470 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
485 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
502 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
716 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
727 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
809 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
H A Dmac.c190 REG_SET_BIT(ah, AR_TIMER_MODE,
201 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
736 REG_SET_BIT(ah, AR_DIAG_SW,
779 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
787 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
951 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
H A Dar5008_phy.c620 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
645 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
663 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
973 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
980 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1132 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1305 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
H A Dhw.c955 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1311 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1342 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1761 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1836 REG_SET_BIT(ah, AR_RTC_RESET,
1839 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1848 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1925 REG_SET_BIT(ah, AR_TXCFG,
1966 REG_SET_BIT(a
[all...]
H A Dar9003_hw.c293 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
H A Dar9003_calib.c42 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
296 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
H A Dar9002_phy.c428 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
H A Dar9003_paprd.c688 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY,
H A Dhw.h98 #define REG_SET_BIT(_a, _r, _f) \ macro

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