Searched refs:R5 (Results 1 - 25 of 41) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/bfin/
H A Dvp3_idct_bfin.S128 * R5 = (Y1,Y7)
133 A1=R7.L*R1.H, A0=R7.H*R1.H (IS) || I0+=4 || R5.H=W[I0];
134 R1=(A1-=R7.H*R1.L), R0=(A0+=R7.L*R1.L) (IS) || R5.L=W[I1--] || R7=[I3++];
154 // R5=(Y1,Y7) R6=(Y5,Y3) // R7=(C1,C7)
155 A1 =R7.L*R5.H, A0 =R7.H*R5.H (IS) || [TMP1]=R2 || R6.H=W[I2--];
156 A1-=R7.H*R5.L, A0+=R7.L*R5.L (IS) || I0-=4 || R7=[I3++];
159 A1 =R7.L*R5.H, A0 =R7.H*R5
[all...]
H A Didct_bfin.S155 * R5 = (Y1,Y7)
160 A1=R7.L*R1.H, A0=R7.H*R1.H (IS) || I0+=4 || R5.H=W[I0];
161 R1=(A1-=R7.H*R1.L), R0=(A0+=R7.L*R1.L) (IS) || R5.L=W[I1--] || R7=[I3++];
181 // R5=(Y1,Y7) R6=(Y5,Y3) // R7=(C1,C7)
182 A1 =R7.L*R5.H, A0 =R7.H*R5.H (IS) || [TMP1]=R2 || R6.H=W[I2--];
183 A1-=R7.H*R5.L, A0+=R7.L*R5.L (IS) || I0-=4 || R7=[I3++];
186 A1 =R7.L*R5.H, A0 =R7.H*R5
[all...]
H A Dpixels_bfin.S27 R5.l = 0x00ff;
28 R5.h = 0x00ff;
38 ppc$0: R2 = MIN(R2, R5) (V);
40 R3 = MIN(R3, R5) (V) || R0 = [I0++];
43 R2 = MIN(R2, R5) (V);
45 R3 = MIN(R3, R5) (V) || R0 = [I0++];
253 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R1 = [I0++] || [I3++] = R4 ; define
254 DISALGNEXCPT || R3 = [I1++] || [I3++] = R5;
256 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R0 = [I0++] || [I3++] = R4 ; define
257 LE$16E: DISALGNEXCPT || R2 = [I1++] || [I3++M2] = R5;
271 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R1 = [I0++] || R6 =[I3++]; define
273 R5 = R5 +|+ R7 || [I3++] = R4; define
276 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R0 = [I0++] || R6 = [I3++]; define
278 R5 = R5 +|+ R7 || [I3++] = R4; define
311 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R1 = [I0++] || [I3++] = R4 ; define
314 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R0 = [I0++] || [I3++] = R4 ; define
329 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R1 = [I0++] || R6 =[I3++]; define
331 R5 = R5 +|+ R7 || [I3++] = R4; define
334 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R0 = [I0++] || R6 = [I3++]; define
336 R5 = R5 +|+ R7 || [I3++] = R4; define
369 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R0 = [I0++] || [I3++] = R4 ; define
384 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R0 = [I0++] || R6 =[I3++]; define
386 R5 = R5 +|+ R7 || [I3++] = R4; define
419 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R0 = [I0++] || [I3++] = R4 ; define
435 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R0 = [I0++] || R6 = [I3++]; define
437 R5 = R5 +|+ R7 || [I3++] = R4; define
[all...]
H A Dfdct_bfin.S60 R0, R1, R2, R3, R4, R5, R6,R7, P0, P1, P2, P3, P4, P5, A0, A1.
70 R6, R5, R4 if modified should be stored and restored.
273 R5.H=(A1-=R0.H*R7.h),R5.L=(A0+=R0.H*R7.h) || R7=[I3++] || NOP;
287 A1=R1.H*R7.L, A0=R1.L*R7.L || W[P0++P3]=R5.L || R2.L=W[I0];
291 /* R2 = (X4, X7) R4 = (X5,X6) R5 = (X1, X0) R6 = (X2,X3). */
301 R2.H=(A1+=R2.L*R7.H),R2.L=(A0-=R2.H*R7.H) || W[P0++P3]=R5.H || R7=[I3++];
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/lib/
H A Ddivsi3.S111 [--SP] = (R7:5); /* Push registers R5-R7 */
116 R5 = R6 >> 31; /* Shift sign to LSB */ define
119 R2 = R2 | R5; /* Shift quotient bit */
125 R0 = R0 << 1 || R5 = [SP];
129 IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
130 R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
132 R5 = R6 >> 31; define
134 BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
135 .Llend: R2 = R2 + R5; /* and then set shifted-in value to
H A Dudivsi3.S116 [--SP] = (R7:5); /* Push registers R5-R7 */
152 R3 = R3 << 1 || R5 = [SP];
156 IF CC R5 = R1; /* and if AQ==1, we'll add it. */
157 R3 = R3 + R5; /* Add/sub divsor to partial remainder */
160 R5 = R7 >> 31; /* Get AQ */ define
161 BITTGL(R5, 0); /* Invert it, to get what we'll shift */
162 .Lulend: R2 = R2 + R5; /* and "shift" it in. */
173 R5 = R0 - R3; /* Z = (dividend - Q * divisor) */ define
174 CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
179 (R7:5) = [SP++]; /* Pop registers R5
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/x86/crypto/
H A Daes-x86_64-asm_64.S40 #define R5 %rsi define
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
136 #define return epilogue(R8,R2,R9,R7,R5,R6,R3,R4,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
140 move_regs(R1,R2,R5,R6)
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/serial/
H A Dpmac_zilog.c160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
190 /* Rewrite R3/R5, this time without enables masked. */
192 write_zsreg(uap, R5, regs[R5]);
592 uap->curregs[R5] |= set_bits;
593 uap->curregs[R5] &= ~clear_bits;
596 write_zsreg(uap, R5, uap->curregs[R5]);
598 set_bits, clear_bits, uap->curregs[R5]);
[all...]
H A Dip22zilog.c191 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
222 /* Rewrite R3/R5, this time without enables masked. */
224 write_zsreg(channel, R5, regs[R5]);
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
673 new_reg = (up->curregs[R5] | set_bit
[all...]
H A Dsunzilog.c209 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
254 /* Rewrite R3/R5, this time without enables masked. */
256 write_zsreg(channel, R5, regs[R5]);
669 up->curregs[R5] |= set_bits;
670 up->curregs[R5] &= ~clear_bits;
671 write_zsreg(channel, R5, up->curregs[R5]);
773 new_reg = (up->curregs[R5] | set_bit
[all...]
H A Dzs.c272 write_zsreg(zport, R5, regs[5] & ~TxENAB);
287 write_zsreg(zport, R5, regs[5]);
404 write_zsreg(zport_a, R5, zport_a->regs[5]);
528 write_zsreg(zport, R5, zport->regs[5]);
793 write_zsreg(zport, R5, zport->regs[5]);
817 write_zsreg(zport, R5, zport->regs[5]);
974 write_zsreg(zport, R5, zport->regs[5]);
1166 write_zsreg(zport, R5, zport->regs[5]);
1178 write_zsreg(zport, R5, zport->regs[5]);
H A Dzs.h64 #define R5 5 macro
H A Dip22zilog.h43 #define R5 5 macro
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/arm/
H A Dsimple_idct_arm.S88 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
89 orr r5, r4, r3 @ R5=R4 | R3
90 orr r5, r5, r2 @ R5=R4 | R3 | R2
91 orrs r6, r5, r1 @ Test R5 | R1 (the aim is to check if everything is null)
95 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
100 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
119 mul r5, r10, r7 @ R5=W5*ROWr16[1]=b2 (ROWr16[1] must be the second arg, to have the possibility to save 1 cycle)
126 mlane r5, r8, r2, r5 @ R5-=W1*ROWr16[3]=b2 (ROWr16[3] must be the second arg, to have the possibility to save 1 cycle)
131 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
139 @@ R5
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/arm/
H A Dsimple_idct_arm.S76 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
77 orr r5, r4, r3 @ R5=R4 | R3
78 orr r5, r5, r2 @ R5=R4 | R3 | R2
79 orrs r6, r5, r1 @ Test R5 | R1 (the aim is to check if everything is null)
83 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
107 mul r5, r10, r7 @ R5=W5*ROWr16[1]=b2 (ROWr16[1] must be the second arg, to have the possibility to save 1 cycle)
114 mlane r5, r8, r2, r5 @ R5-=W1*ROWr16[3]=b2 (ROWr16[3] must be the second arg, to have the possibility to save 1 cycle)
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Dentry.S372 R5 = [P4]; /* Control Register*/ define
373 BITCLR(R5,ENICPLB_P);
375 [P4] = R5;
380 R5 = [P4]; define
381 BITCLR(R5,ENDCPLB_P);
383 [P4] = R5;
1132 R5 = [P4]; /* Control Register*/ define
1133 BITCLR(R5,ENICPLB_P);
1135 [P4] = R5;
1140 R5 define
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/video/
H A Dwm8739.c51 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator in enum:__anon12292
253 wm8739_write(sd, R5, 0x000);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/hamradio/
H A Dscc.c803 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */
935 or(scc,R5, TxENAB);
936 scc->wreg[R5] |= RTS;
938 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */
941 cl(scc,R5,RTS|TxENAB);
969 or(scc,R5, TxENAB);
970 scc->wreg[R5] |= RTS;
972 or(scc,R5,RTS|TxENAB); /* enable tx */
975 cl(scc,R5,RTS|TxENAB); /* disable tx */
1106 if ( (grp1 & TXGROUP) && (scc2->wreg[R5]
[all...]
H A Dz8530.h11 #define R5 5 macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/m32r/kernel/
H A Dentry.S84 #define R5(reg) @(0x04,reg) define
253 ld r5, R5(sp)
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/timemachine/openssl-0.9.8e/crypto/md5/asm/
H A Dmd5-sparcv9.S55 #define R5 %l5 define
71 #define Aval R5 /* those not used at the end of the last round */
189 LOAD X(5),R5
203 add T1,R5,T1 !=
401 !pre-LOADed X(5),R5
414 add T1,R5,T1
569 !pre-LOADed X(5),R5
583 add T1,R5,T1
820 !pre-LOADed X(5),R5
832 add T1,R5,T
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libswscale/x86/
H A Dinput.asm156 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
167 movd m3, [srcq+14] ; (byte) { R4, B5, G5, R5 }
171 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
176 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
182 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
258 movd m5, [srcq+14] ; (byte) { R4, B5, G5, R5 }
270 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
277 punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
280 punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
284 pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*B
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/x86/
H A Dvp3dsp.asm242 paddsw m5, m6 ; r5 = R5 = F. + B..
270 paddsw m6, OC_8 ; adjust R6 (and R5) for shift
272 paddsw m5, m6 ; r5 = R5 = F. + B..
328 punpckhdq m5, m6 ; r5 = h1 g1 f1 e1 = R5
448 ADD(m6) ; Adjust R6 and R5 before shifting
450 paddsw m5, m6 ; xmm5 = F. + B.. = R5
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/x86/
H A Dvp3dsp.asm244 paddsw m5, m6 ; r5 = R5 = F. + B..
272 paddsw m6, OC_8 ; adjust R6 (and R5) for shift
274 paddsw m5, m6 ; r5 = R5 = F. + B..
330 punpckhdq m5, m6 ; r5 = h1 g1 f1 e1 = R5
482 ADD(m6) ; Adjust R6 and R5 before shifting
484 paddsw m5, m6 ; xmm5 = F. + B.. = R5
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wan/
H A Dz85230.h30 #define R5 5 macro
184 #define PRIME 1 /* R5' etc register access (Z85C30/230 only) */

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