Lines Matching refs:R5
160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
190 /* Rewrite R3/R5, this time without enables masked. */
192 write_zsreg(uap, R5, regs[R5]);
592 uap->curregs[R5] |= set_bits;
593 uap->curregs[R5] &= ~clear_bits;
596 write_zsreg(uap, R5, uap->curregs[R5]);
598 set_bits, clear_bits, uap->curregs[R5]);
749 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
750 if (new_reg != uap->curregs[R5]) {
751 uap->curregs[R5] = new_reg;
758 write_zsreg(uap, R5, uap->curregs[R5]);
884 uap->curregs[R5] = Tx8 | RTS;
886 uap->curregs[R5] |= DTR;
901 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
911 uap->curregs[R5] |= DTR;
912 write_zsreg(uap, R5, uap->curregs[R5]);
915 uap->curregs[R5] &= ~DTR;
916 write_zsreg(uap, R5, uap->curregs[R5]);
1024 uap->curregs[R5] &= ~TxENABLE;
1027 uap->curregs[R5] &= ~SND_BRK;
1216 uap->curregs[R5] |= DTR;
1217 write_zsreg(uap, R5, uap->curregs[R5]);
1266 uap->curregs[R5] &= ~DTR;
1267 write_zsreg(uap, R5, uap->curregs[R5]);
1650 uap->curregs[R5] &= ~TxENABLE;
1654 uap->curregs[R5] &= ~SND_BRK;
2097 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);