Searched refs:EFX_SET_OWORD_FIELD (Results 1 - 7 of 7) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/sfc/
H A Dfalcon_xmac.c39 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
40 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
41 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
42 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
43 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
44 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
45 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
46 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
123 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
124 EFX_SET_OWORD_FIELD(re
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H A Dfalcon.c61 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
71 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
485 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
489 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
490 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
491 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
546 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
580 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
592 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
595 EFX_SET_OWORD_FIELD(re
[all...]
H A Dfalcon_gmac.c104 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode);
105 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !link_state->fd);
106 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !link_state->fd);
107 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0);
H A Dsiena.c317 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
324 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
325 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
329 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
330 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
334 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
335 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
336 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
H A Dnic.c434 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
435 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
661 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
1632 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1642 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1643 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1644 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1645 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
1646 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1648 EFX_SET_OWORD_FIELD(tem
[all...]
H A Dfalcon_boards.c320 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);
323 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);
324 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,
H A Dbitfield.h518 #define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD64 macro
521 #define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD32 macro

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