Searched refs:DIV4 (Results 1 - 11 of 11) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c117 #define DIV4(_reg, _bit, _mask, _flags) \ macro
123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
134 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
140 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
141 [DIV4_SIUB] = DIV4(SCLKBC
[all...]
H A Dclock-sh7785.c69 #define DIV4(_bit, _mask, _flags) \ macro
73 [DIV4_P] = DIV4(0, 0x0f80, 0),
74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
75 [DIV4_GA] = DIV4(8, 0x0030, 0),
76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
126 /* DIV4 clock
[all...]
H A Dclock-sh7786.c70 #define DIV4(_bit, _mask, _flags) \ macro
74 [DIV4_P] = DIV4(0, 0x0b40, 0),
75 [DIV4_DU] = DIV4(4, 0x0010, 0),
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
135 /* DIV4 clocks */
H A Dclock-sh7366.c120 #define DIV4(_reg, _bit, _mask, _flags) \ macro
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
204 /* DIV4 clock
[all...]
H A Dclock-sh7723.c120 #define DIV4(_reg, _bit, _mask, _flags) \ macro
124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
142 [DIV4_SIUB] = DIV4(SCLKBC
[all...]
H A Dclock-sh7343.c117 #define DIV4(_reg, _bit, _mask, _flags) \ macro
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
206 /* DIV4 clock
[all...]
H A Dclock-sh7724.c146 #define DIV4(_reg, _bit, _mask, _flags) \ macro
150 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
151 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
234 /* DIV4 clocks */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-shmobile/
H A Dclock-sh7367.c179 #define DIV4(_reg, _bit, _mask, _flags) \ macro
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
191 [DIV4_HP] = DIV4(SYFRQC
[all...]
H A Dclock-sh7377.c189 #define DIV4(_reg, _bit, _mask, _flags) \ macro
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
197 [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
198 [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
199 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
200 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
201 [DIV4_HP] = DIV4(SYFRQC
[all...]
H A Dclock-sh7372.c338 #define DIV4(_reg, _bit, _mask, _flags) \ macro
342 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
343 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
344 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
345 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
346 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
347 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
348 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
349 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
350 [DIV4_HP] = DIV4(FRQCR
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/
H A Dplatinumfb.h70 #define DIV4 0x40 macro
169 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
181 {{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }}
193 {{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }}
205 {{ 54, 3 + DIV4 }, { 95, 1 + DIV8 }}
217 {{ 54, 3 + DIV4 }, { 88, 1 + DIV8 }}
241 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
253 {{ 99, 4 + DIV8 }, { 42, 5 + DIV4 }}
265 {{ 26, 0 + DIV8 }, { 14, 2 + DIV4 }}

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