Lines Matching refs:DIV4
338 #define DIV4(_reg, _bit, _mask, _flags) \
342 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
343 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
344 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
345 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
346 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
347 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
348 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
349 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
350 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
351 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
352 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
353 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
354 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
355 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
356 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
463 /* DIV4 clocks */