Lines Matching refs:DIV4
120 #define DIV4(_reg, _bit, _mask, _flags) \
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
204 /* DIV4 clocks */