/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/ |
H A D | clock2430_data.c | 495 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 522 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 551 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 586 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 745 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 758 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL [all...] |
H A D | clock2420_data.c | 549 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 576 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 605 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 641 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 770 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL [all...] |
H A D | pm24xx.c | 68 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 69 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 94 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 95 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 147 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); 148 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 170 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 181 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 187 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 210 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST [all...] |
H A D | prcm.c | 330 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 332 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 346 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); 348 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); 350 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); 372 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); 388 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); 390 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); 392 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); 430 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL [all...] |
H A D | clock2430.c | 48 *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST);
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H A D | powerdomains24xx.h | 69 .prcm_offs = CORE_MOD,
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H A D | clock3xxx_data.c | 710 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1150 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1167 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1315 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1325 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1345 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1364 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1376 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN [all...] |
H A D | pm34xx.c | 238 c += prcm_clear_mod_irqs(CORE_MOD, 1); 241 c += prcm_clear_mod_irqs(CORE_MOD, 3); 746 CORE_MOD, OMAP2_RM_RSTCTRL); 747 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 799 CORE_MOD, CM_AUTOIDLE1); 807 CORE_MOD, CM_AUTOIDLE2); 813 CORE_MOD, CM_AUTOIDLE3); 932 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 933 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 938 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTS [all...] |
H A D | clockdomains.h | 472 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 482 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 492 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 556 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 567 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 578 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 660 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 669 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), 679 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
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H A D | clkt2xxx_virt_prcm_set.c | 120 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; 121 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
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H A D | powerdomains34xx.h | 86 .prcm_offs = CORE_MOD, 106 .prcm_offs = CORE_MOD,
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H A D | pm-debug.c | 69 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); 71 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); 144 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c }, 158 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
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H A D | serial.c | 489 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; 515 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); 516 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); 518 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); 519 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
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H A D | sram34xx.S | 269 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) 271 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
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H A D | prcm-common.h | 30 #define CORE_MOD 0x200 macro
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H A D | control.c | 239 cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
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H A D | sleep34xx.S | 38 #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 44 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
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