1/* 2 * OMAP3 powerdomain definitions 3 * 4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 5 * Copyright (C) 2007-2010 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * Debugging and integration fixes by Jouni H��gander 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX 16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX 17 18/* 19 * N.B. If powerdomains are added or removed from this file, update 20 * the array in mach-omap2/powerdomains.h. 21 */ 22 23#include <plat/powerdomain.h> 24 25#include "prcm-common.h" 26#include "prm.h" 27#include "prm-regbits-34xx.h" 28#include "cm.h" 29#include "cm-regbits-34xx.h" 30 31/* 32 * 34XX-specific powerdomains, dependencies 33 */ 34 35#ifdef CONFIG_ARCH_OMAP3 36 37/* 38 * Powerdomains 39 */ 40 41static struct powerdomain iva2_pwrdm = { 42 .name = "iva2_pwrdm", 43 .prcm_offs = OMAP3430_IVA2_MOD, 44 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 45 .pwrsts = PWRSTS_OFF_RET_ON, 46 .pwrsts_logic_ret = PWRSTS_OFF_RET, 47 .banks = 4, 48 .pwrsts_mem_ret = { 49 [0] = PWRSTS_OFF_RET, 50 [1] = PWRSTS_OFF_RET, 51 [2] = PWRSTS_OFF_RET, 52 [3] = PWRSTS_OFF_RET, 53 }, 54 .pwrsts_mem_on = { 55 [0] = PWRDM_POWER_ON, 56 [1] = PWRDM_POWER_ON, 57 [2] = PWRSTS_OFF_ON, 58 [3] = PWRDM_POWER_ON, 59 }, 60}; 61 62static struct powerdomain mpu_3xxx_pwrdm = { 63 .name = "mpu_pwrdm", 64 .prcm_offs = MPU_MOD, 65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 66 .pwrsts = PWRSTS_OFF_RET_ON, 67 .pwrsts_logic_ret = PWRSTS_OFF_RET, 68 .flags = PWRDM_HAS_MPU_QUIRK, 69 .banks = 1, 70 .pwrsts_mem_ret = { 71 [0] = PWRSTS_OFF_RET, 72 }, 73 .pwrsts_mem_on = { 74 [0] = PWRSTS_OFF_ON, 75 }, 76}; 77 78/* 79 * The USBTLL Save-and-Restore mechanism is broken on 80 * 3430s upto ES3.0 and 3630ES1.0. Hence this feature 81 * needs to be disabled on these chips. 82 * Refer: 3430 errata ID i459 and 3630 errata ID i579 83 */ 84static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { 85 .name = "core_pwrdm", 86 .prcm_offs = CORE_MOD, 87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | 88 CHIP_IS_OMAP3430ES2 | 89 CHIP_IS_OMAP3430ES3_0 | 90 CHIP_IS_OMAP3630ES1), 91 .pwrsts = PWRSTS_OFF_RET_ON, 92 .pwrsts_logic_ret = PWRSTS_OFF_RET, 93 .banks = 2, 94 .pwrsts_mem_ret = { 95 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 96 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 97 }, 98 .pwrsts_mem_on = { 99 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 100 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 101 }, 102}; 103 104static struct powerdomain core_3xxx_es3_1_pwrdm = { 105 .name = "core_pwrdm", 106 .prcm_offs = CORE_MOD, 107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | 108 CHIP_GE_OMAP3630ES1_1), 109 .pwrsts = PWRSTS_OFF_RET_ON, 110 .pwrsts_logic_ret = PWRSTS_OFF_RET, 111 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ 112 .banks = 2, 113 .pwrsts_mem_ret = { 114 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 115 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ 116 }, 117 .pwrsts_mem_on = { 118 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 119 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 120 }, 121}; 122 123static struct powerdomain dss_pwrdm = { 124 .name = "dss_pwrdm", 125 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 126 .prcm_offs = OMAP3430_DSS_MOD, 127 .pwrsts = PWRSTS_OFF_RET_ON, 128 .pwrsts_logic_ret = PWRDM_POWER_RET, 129 .banks = 1, 130 .pwrsts_mem_ret = { 131 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 132 }, 133 .pwrsts_mem_on = { 134 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 135 }, 136}; 137 138/* 139 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a 140 * possible SGX powerstate, the SGX device itself does not support 141 * retention. 142 */ 143static struct powerdomain sgx_pwrdm = { 144 .name = "sgx_pwrdm", 145 .prcm_offs = OMAP3430ES2_SGX_MOD, 146 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 147 .pwrsts = PWRSTS_OFF_ON, 148 .pwrsts_logic_ret = PWRDM_POWER_RET, 149 .banks = 1, 150 .pwrsts_mem_ret = { 151 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 152 }, 153 .pwrsts_mem_on = { 154 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 155 }, 156}; 157 158static struct powerdomain cam_pwrdm = { 159 .name = "cam_pwrdm", 160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 161 .prcm_offs = OMAP3430_CAM_MOD, 162 .pwrsts = PWRSTS_OFF_RET_ON, 163 .pwrsts_logic_ret = PWRDM_POWER_RET, 164 .banks = 1, 165 .pwrsts_mem_ret = { 166 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 167 }, 168 .pwrsts_mem_on = { 169 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 170 }, 171}; 172 173static struct powerdomain per_pwrdm = { 174 .name = "per_pwrdm", 175 .prcm_offs = OMAP3430_PER_MOD, 176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 177 .pwrsts = PWRSTS_OFF_RET_ON, 178 .pwrsts_logic_ret = PWRSTS_OFF_RET, 179 .banks = 1, 180 .pwrsts_mem_ret = { 181 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 182 }, 183 .pwrsts_mem_on = { 184 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 185 }, 186}; 187 188static struct powerdomain emu_pwrdm = { 189 .name = "emu_pwrdm", 190 .prcm_offs = OMAP3430_EMU_MOD, 191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 192}; 193 194static struct powerdomain neon_pwrdm = { 195 .name = "neon_pwrdm", 196 .prcm_offs = OMAP3430_NEON_MOD, 197 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 198 .pwrsts = PWRSTS_OFF_RET_ON, 199 .pwrsts_logic_ret = PWRDM_POWER_RET, 200}; 201 202static struct powerdomain usbhost_pwrdm = { 203 .name = "usbhost_pwrdm", 204 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 205 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 206 .pwrsts = PWRSTS_OFF_RET_ON, 207 .pwrsts_logic_ret = PWRDM_POWER_RET, 208 /* 209 * REVISIT: Enabling usb host save and restore mechanism seems to 210 * leave the usb host domain permanently in ACTIVE mode after 211 * changing the usb host power domain state from OFF to active once. 212 * Disabling for now. 213 */ 214 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ 215 .banks = 1, 216 .pwrsts_mem_ret = { 217 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 218 }, 219 .pwrsts_mem_on = { 220 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 221 }, 222}; 223 224static struct powerdomain dpll1_pwrdm = { 225 .name = "dpll1_pwrdm", 226 .prcm_offs = MPU_MOD, 227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 228}; 229 230static struct powerdomain dpll2_pwrdm = { 231 .name = "dpll2_pwrdm", 232 .prcm_offs = OMAP3430_IVA2_MOD, 233 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 234}; 235 236static struct powerdomain dpll3_pwrdm = { 237 .name = "dpll3_pwrdm", 238 .prcm_offs = PLL_MOD, 239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 240}; 241 242static struct powerdomain dpll4_pwrdm = { 243 .name = "dpll4_pwrdm", 244 .prcm_offs = PLL_MOD, 245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 246}; 247 248static struct powerdomain dpll5_pwrdm = { 249 .name = "dpll5_pwrdm", 250 .prcm_offs = PLL_MOD, 251 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 252}; 253 254 255#endif /* CONFIG_ARCH_OMAP3 */ 256 257 258#endif 259