1/* 2 * arch/arm/mach-omap2/serial.c 3 * 4 * OMAP2 serial support. 5 * 6 * Copyright (C) 2005-2008 Nokia Corporation 7 * Author: Paul Mundt <paul.mundt@nokia.com> 8 * 9 * Major rework for PM support by Kevin Hilman 10 * 11 * Based off of arch/arm/mach-omap/omap1/serial.c 12 * 13 * Copyright (C) 2009 Texas Instruments 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20#include <linux/kernel.h> 21#include <linux/init.h> 22#include <linux/serial_8250.h> 23#include <linux/serial_reg.h> 24#include <linux/clk.h> 25#include <linux/io.h> 26#include <linux/delay.h> 27 28#include <plat/common.h> 29#include <plat/board.h> 30#include <plat/clock.h> 31#include <plat/control.h> 32 33#include "prm.h" 34#include "pm.h" 35#include "prm-regbits-34xx.h" 36 37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 38#define UART_OMAP_WER 0x17 /* Wake-up enable register */ 39 40#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) 41#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) 42 43/* 44 * NOTE: By default the serial timeout is disabled as it causes lost characters 45 * over the serial ports. This means that the UART clocks will stay on until 46 * disabled via sysfs. This also causes that any deeper omap sleep states are 47 * blocked. 48 */ 49#define DEFAULT_TIMEOUT 0 50 51struct omap_uart_state { 52 int num; 53 int can_sleep; 54 struct timer_list timer; 55 u32 timeout; 56 57 void __iomem *wk_st; 58 void __iomem *wk_en; 59 u32 wk_mask; 60 u32 padconf; 61 62 struct clk *ick; 63 struct clk *fck; 64 int clocked; 65 66 struct plat_serial8250_port *p; 67 struct list_head node; 68 struct platform_device pdev; 69 70 u32 errata; 71#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 72 int context_valid; 73 74 /* Registers to be saved/restored for OFF-mode */ 75 u16 dll; 76 u16 dlh; 77 u16 ier; 78 u16 sysc; 79 u16 scr; 80 u16 wer; 81 u16 mcr; 82#endif 83}; 84 85static LIST_HEAD(uart_list); 86 87static struct plat_serial8250_port serial_platform_data0[] = { 88 { 89 .irq = 72, 90 .flags = UPF_BOOT_AUTOCONF, 91 .iotype = UPIO_MEM, 92 .regshift = 2, 93 .uartclk = OMAP24XX_BASE_BAUD * 16, 94 }, { 95 .flags = 0 96 } 97}; 98 99static struct plat_serial8250_port serial_platform_data1[] = { 100 { 101 .irq = 73, 102 .flags = UPF_BOOT_AUTOCONF, 103 .iotype = UPIO_MEM, 104 .regshift = 2, 105 .uartclk = OMAP24XX_BASE_BAUD * 16, 106 }, { 107 .flags = 0 108 } 109}; 110 111static struct plat_serial8250_port serial_platform_data2[] = { 112 { 113 .irq = 74, 114 .flags = UPF_BOOT_AUTOCONF, 115 .iotype = UPIO_MEM, 116 .regshift = 2, 117 .uartclk = OMAP24XX_BASE_BAUD * 16, 118 }, { 119 .flags = 0 120 } 121}; 122 123static struct plat_serial8250_port serial_platform_data3[] = { 124 { 125 .irq = 70, 126 .flags = UPF_BOOT_AUTOCONF, 127 .iotype = UPIO_MEM, 128 .regshift = 2, 129 .uartclk = OMAP24XX_BASE_BAUD * 16, 130 }, { 131 .flags = 0 132 } 133}; 134 135void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) 136{ 137 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; 138 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; 139 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; 140 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; 141} 142 143static inline unsigned int __serial_read_reg(struct uart_port *up, 144 int offset) 145{ 146 offset <<= up->regshift; 147 return (unsigned int)__raw_readb(up->membase + offset); 148} 149 150static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, 151 int offset) 152{ 153 offset <<= up->regshift; 154 return (unsigned int)__raw_readb(up->membase + offset); 155} 156 157static inline void __serial_write_reg(struct uart_port *up, int offset, 158 int value) 159{ 160 offset <<= up->regshift; 161 __raw_writeb(value, up->membase + offset); 162} 163 164static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, 165 int value) 166{ 167 offset <<= p->regshift; 168 __raw_writeb(value, p->membase + offset); 169} 170 171/* 172 * Internal UARTs need to be initialized for the 8250 autoconfig to work 173 * properly. Note that the TX watermark initialization may not be needed 174 * once the 8250.c watermark handling code is merged. 175 */ 176static inline void __init omap_uart_reset(struct omap_uart_state *uart) 177{ 178 struct plat_serial8250_port *p = uart->p; 179 180 serial_write_reg(p, UART_OMAP_MDR1, 0x07); 181 serial_write_reg(p, UART_OMAP_SCR, 0x08); 182 serial_write_reg(p, UART_OMAP_MDR1, 0x00); 183 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); 184} 185 186#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) 187 188static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, 189 u8 fcr_val) 190{ 191 struct plat_serial8250_port *p = uart->p; 192 u8 timeout = 255; 193 194 serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); 195 udelay(2); 196 serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | 197 UART_FCR_CLEAR_RCVR); 198 /* 199 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 200 * TX_FIFO_E bit is 1. 201 */ 202 while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & 203 (UART_LSR_THRE | UART_LSR_DR))) { 204 timeout--; 205 if (!timeout) { 206 /* Should *never* happen. we warn and carry on */ 207 dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", 208 serial_read_reg(p, UART_LSR)); 209 break; 210 } 211 udelay(1); 212 } 213} 214 215static void omap_uart_save_context(struct omap_uart_state *uart) 216{ 217 u16 lcr = 0; 218 struct plat_serial8250_port *p = uart->p; 219 220 if (!enable_off_mode) 221 return; 222 223 lcr = serial_read_reg(p, UART_LCR); 224 serial_write_reg(p, UART_LCR, 0xBF); 225 uart->dll = serial_read_reg(p, UART_DLL); 226 uart->dlh = serial_read_reg(p, UART_DLM); 227 serial_write_reg(p, UART_LCR, lcr); 228 uart->ier = serial_read_reg(p, UART_IER); 229 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); 230 uart->scr = serial_read_reg(p, UART_OMAP_SCR); 231 uart->wer = serial_read_reg(p, UART_OMAP_WER); 232 serial_write_reg(p, UART_LCR, 0x80); 233 uart->mcr = serial_read_reg(p, UART_MCR); 234 serial_write_reg(p, UART_LCR, lcr); 235 236 uart->context_valid = 1; 237} 238 239static void omap_uart_restore_context(struct omap_uart_state *uart) 240{ 241 u16 efr = 0; 242 struct plat_serial8250_port *p = uart->p; 243 244 if (!enable_off_mode) 245 return; 246 247 if (!uart->context_valid) 248 return; 249 250 uart->context_valid = 0; 251 252 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 253 omap_uart_mdr1_errataset(uart, 0x07, 0xA0); 254 else 255 serial_write_reg(p, UART_OMAP_MDR1, 0x7); 256 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 257 efr = serial_read_reg(p, UART_EFR); 258 serial_write_reg(p, UART_EFR, UART_EFR_ECB); 259 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ 260 serial_write_reg(p, UART_IER, 0x0); 261 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 262 serial_write_reg(p, UART_DLL, uart->dll); 263 serial_write_reg(p, UART_DLM, uart->dlh); 264 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ 265 serial_write_reg(p, UART_IER, uart->ier); 266 serial_write_reg(p, UART_LCR, 0x80); 267 serial_write_reg(p, UART_MCR, uart->mcr); 268 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ 269 serial_write_reg(p, UART_EFR, efr); 270 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); 271 serial_write_reg(p, UART_OMAP_SCR, uart->scr); 272 serial_write_reg(p, UART_OMAP_WER, uart->wer); 273 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); 274 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 275 omap_uart_mdr1_errataset(uart, 0x00, 0xA1); 276 else 277 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ 278} 279#else 280static inline void omap_uart_save_context(struct omap_uart_state *uart) {} 281static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} 282#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ 283 284static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) 285{ 286 if (uart->clocked) 287 return; 288 289 clk_enable(uart->ick); 290 clk_enable(uart->fck); 291 uart->clocked = 1; 292 omap_uart_restore_context(uart); 293} 294 295#ifdef CONFIG_PM 296 297static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) 298{ 299 if (!uart->clocked) 300 return; 301 302 omap_uart_save_context(uart); 303 uart->clocked = 0; 304 clk_disable(uart->ick); 305 clk_disable(uart->fck); 306} 307 308static void omap_uart_enable_wakeup(struct omap_uart_state *uart) 309{ 310 /* Set wake-enable bit */ 311 if (uart->wk_en && uart->wk_mask) { 312 u32 v = __raw_readl(uart->wk_en); 313 v |= uart->wk_mask; 314 __raw_writel(v, uart->wk_en); 315 } 316 317 /* Ensure IOPAD wake-enables are set */ 318 if (cpu_is_omap34xx() && uart->padconf) { 319 u16 v = omap_ctrl_readw(uart->padconf); 320 v |= OMAP3_PADCONF_WAKEUPENABLE0; 321 omap_ctrl_writew(v, uart->padconf); 322 } 323} 324 325static void omap_uart_disable_wakeup(struct omap_uart_state *uart) 326{ 327 /* Clear wake-enable bit */ 328 if (uart->wk_en && uart->wk_mask) { 329 u32 v = __raw_readl(uart->wk_en); 330 v &= ~uart->wk_mask; 331 __raw_writel(v, uart->wk_en); 332 } 333 334 /* Ensure IOPAD wake-enables are cleared */ 335 if (cpu_is_omap34xx() && uart->padconf) { 336 u16 v = omap_ctrl_readw(uart->padconf); 337 v &= ~OMAP3_PADCONF_WAKEUPENABLE0; 338 omap_ctrl_writew(v, uart->padconf); 339 } 340} 341 342static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, 343 int enable) 344{ 345 struct plat_serial8250_port *p = uart->p; 346 u16 sysc; 347 348 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; 349 if (enable) 350 sysc |= 0x2 << 3; 351 else 352 sysc |= 0x1 << 3; 353 354 serial_write_reg(p, UART_OMAP_SYSC, sysc); 355} 356 357static void omap_uart_block_sleep(struct omap_uart_state *uart) 358{ 359 omap_uart_enable_clocks(uart); 360 361 omap_uart_smart_idle_enable(uart, 0); 362 uart->can_sleep = 0; 363 if (uart->timeout) 364 mod_timer(&uart->timer, jiffies + uart->timeout); 365 else 366 del_timer(&uart->timer); 367} 368 369static void omap_uart_allow_sleep(struct omap_uart_state *uart) 370{ 371 if (device_may_wakeup(&uart->pdev.dev)) 372 omap_uart_enable_wakeup(uart); 373 else 374 omap_uart_disable_wakeup(uart); 375 376 if (!uart->clocked) 377 return; 378 379 omap_uart_smart_idle_enable(uart, 1); 380 uart->can_sleep = 1; 381 del_timer(&uart->timer); 382} 383 384static void omap_uart_idle_timer(unsigned long data) 385{ 386 struct omap_uart_state *uart = (struct omap_uart_state *)data; 387 388 omap_uart_allow_sleep(uart); 389} 390 391void omap_uart_prepare_idle(int num) 392{ 393 struct omap_uart_state *uart; 394 395 list_for_each_entry(uart, &uart_list, node) { 396 if (num == uart->num && uart->can_sleep) { 397 omap_uart_disable_clocks(uart); 398 return; 399 } 400 } 401} 402 403void omap_uart_resume_idle(int num) 404{ 405 struct omap_uart_state *uart; 406 407 list_for_each_entry(uart, &uart_list, node) { 408 if (num == uart->num) { 409 omap_uart_enable_clocks(uart); 410 411 /* Check for IO pad wakeup */ 412 if (cpu_is_omap34xx() && uart->padconf) { 413 u16 p = omap_ctrl_readw(uart->padconf); 414 415 if (p & OMAP3_PADCONF_WAKEUPEVENT0) 416 omap_uart_block_sleep(uart); 417 } 418 419 /* Check for normal UART wakeup */ 420 if (__raw_readl(uart->wk_st) & uart->wk_mask) 421 omap_uart_block_sleep(uart); 422 return; 423 } 424 } 425} 426 427void omap_uart_prepare_suspend(void) 428{ 429 struct omap_uart_state *uart; 430 431 list_for_each_entry(uart, &uart_list, node) { 432 omap_uart_allow_sleep(uart); 433 } 434} 435 436int omap_uart_can_sleep(void) 437{ 438 struct omap_uart_state *uart; 439 int can_sleep = 1; 440 441 list_for_each_entry(uart, &uart_list, node) { 442 if (!uart->clocked) 443 continue; 444 445 if (!uart->can_sleep) { 446 can_sleep = 0; 447 continue; 448 } 449 450 /* This UART can now safely sleep. */ 451 omap_uart_allow_sleep(uart); 452 } 453 454 return can_sleep; 455} 456 457/** 458 * omap_uart_interrupt() 459 * 460 * This handler is used only to detect that *any* UART interrupt has 461 * occurred. It does _nothing_ to handle the interrupt. Rather, 462 * any UART interrupt will trigger the inactivity timer so the 463 * UART will not idle or sleep for its timeout period. 464 * 465 **/ 466static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) 467{ 468 struct omap_uart_state *uart = dev_id; 469 470 omap_uart_block_sleep(uart); 471 472 return IRQ_NONE; 473} 474 475static void omap_uart_idle_init(struct omap_uart_state *uart) 476{ 477 struct plat_serial8250_port *p = uart->p; 478 int ret; 479 480 uart->can_sleep = 0; 481 uart->timeout = DEFAULT_TIMEOUT; 482 setup_timer(&uart->timer, omap_uart_idle_timer, 483 (unsigned long) uart); 484 if (uart->timeout) 485 mod_timer(&uart->timer, jiffies + uart->timeout); 486 omap_uart_smart_idle_enable(uart, 0); 487 488 if (cpu_is_omap34xx()) { 489 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; 490 u32 wk_mask = 0; 491 u32 padconf = 0; 492 493 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); 494 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); 495 switch (uart->num) { 496 case 0: 497 wk_mask = OMAP3430_ST_UART1_MASK; 498 padconf = 0x182; 499 break; 500 case 1: 501 wk_mask = OMAP3430_ST_UART2_MASK; 502 padconf = 0x17a; 503 break; 504 case 2: 505 wk_mask = OMAP3430_ST_UART3_MASK; 506 padconf = 0x19e; 507 break; 508 } 509 uart->wk_mask = wk_mask; 510 uart->padconf = padconf; 511 } else if (cpu_is_omap24xx()) { 512 u32 wk_mask = 0; 513 514 if (cpu_is_omap2430()) { 515 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); 516 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); 517 } else if (cpu_is_omap2420()) { 518 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); 519 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); 520 } 521 switch (uart->num) { 522 case 0: 523 wk_mask = OMAP24XX_ST_UART1_MASK; 524 break; 525 case 1: 526 wk_mask = OMAP24XX_ST_UART2_MASK; 527 break; 528 case 2: 529 wk_mask = OMAP24XX_ST_UART3_MASK; 530 break; 531 } 532 uart->wk_mask = wk_mask; 533 } else { 534 uart->wk_en = NULL; 535 uart->wk_st = NULL; 536 uart->wk_mask = 0; 537 uart->padconf = 0; 538 } 539 540 p->irqflags |= IRQF_SHARED; 541 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, 542 "serial idle", (void *)uart); 543 WARN_ON(ret); 544} 545 546void omap_uart_enable_irqs(int enable) 547{ 548 int ret; 549 struct omap_uart_state *uart; 550 551 list_for_each_entry(uart, &uart_list, node) { 552 if (enable) 553 ret = request_irq(uart->p->irq, omap_uart_interrupt, 554 IRQF_SHARED, "serial idle", (void *)uart); 555 else 556 free_irq(uart->p->irq, (void *)uart); 557 } 558} 559 560static ssize_t sleep_timeout_show(struct device *dev, 561 struct device_attribute *attr, 562 char *buf) 563{ 564 struct platform_device *pdev = container_of(dev, 565 struct platform_device, dev); 566 struct omap_uart_state *uart = container_of(pdev, 567 struct omap_uart_state, pdev); 568 569 return sprintf(buf, "%u\n", uart->timeout / HZ); 570} 571 572static ssize_t sleep_timeout_store(struct device *dev, 573 struct device_attribute *attr, 574 const char *buf, size_t n) 575{ 576 struct platform_device *pdev = container_of(dev, 577 struct platform_device, dev); 578 struct omap_uart_state *uart = container_of(pdev, 579 struct omap_uart_state, pdev); 580 unsigned int value; 581 582 if (sscanf(buf, "%u", &value) != 1) { 583 dev_err(dev, "sleep_timeout_store: Invalid value\n"); 584 return -EINVAL; 585 } 586 587 uart->timeout = value * HZ; 588 if (uart->timeout) 589 mod_timer(&uart->timer, jiffies + uart->timeout); 590 else 591 /* A zero value means disable timeout feature */ 592 omap_uart_block_sleep(uart); 593 594 return n; 595} 596 597static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, 598 sleep_timeout_store); 599#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) 600#else 601static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} 602#define DEV_CREATE_FILE(dev, attr) 603#endif /* CONFIG_PM */ 604 605static struct omap_uart_state omap_uart[] = { 606 { 607 .pdev = { 608 .name = "serial8250", 609 .id = PLAT8250_DEV_PLATFORM, 610 .dev = { 611 .platform_data = serial_platform_data0, 612 }, 613 }, 614 }, { 615 .pdev = { 616 .name = "serial8250", 617 .id = PLAT8250_DEV_PLATFORM1, 618 .dev = { 619 .platform_data = serial_platform_data1, 620 }, 621 }, 622 }, { 623 .pdev = { 624 .name = "serial8250", 625 .id = PLAT8250_DEV_PLATFORM2, 626 .dev = { 627 .platform_data = serial_platform_data2, 628 }, 629 }, 630 }, 631#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 632 { 633 .pdev = { 634 .name = "serial8250", 635 .id = 3, 636 .dev = { 637 .platform_data = serial_platform_data3, 638 }, 639 }, 640 }, 641#endif 642}; 643 644/* 645 * Override the default 8250 read handler: mem_serial_in() 646 * Empty RX fifo read causes an abort on omap3630 and omap4 647 * This function makes sure that an empty rx fifo is not read on these silicons 648 * (OMAP1/2/3430 are not affected) 649 */ 650static unsigned int serial_in_override(struct uart_port *up, int offset) 651{ 652 if (UART_RX == offset) { 653 unsigned int lsr; 654 lsr = __serial_read_reg(up, UART_LSR); 655 if (!(lsr & UART_LSR_DR)) 656 return -EPERM; 657 } 658 659 return __serial_read_reg(up, offset); 660} 661 662static void serial_out_override(struct uart_port *up, int offset, int value) 663{ 664 unsigned int status, tmout = 10000; 665 666 status = __serial_read_reg(up, UART_LSR); 667 while (!(status & UART_LSR_THRE)) { 668 /* Wait up to 10ms for the character(s) to be sent. */ 669 if (--tmout == 0) 670 break; 671 udelay(1); 672 status = __serial_read_reg(up, UART_LSR); 673 } 674 __serial_write_reg(up, offset, value); 675} 676void __init omap_serial_early_init(void) 677{ 678 int i, nr_ports; 679 char name[16]; 680 681 if (!(cpu_is_omap3630() || cpu_is_omap4430())) 682 nr_ports = 3; 683 else 684 nr_ports = ARRAY_SIZE(omap_uart); 685 686 /* 687 * Make sure the serial ports are muxed on at this point. 688 * You have to mux them off in device drivers later on 689 * if not needed. 690 */ 691 692 for (i = 0; i < nr_ports; i++) { 693 struct omap_uart_state *uart = &omap_uart[i]; 694 struct platform_device *pdev = &uart->pdev; 695 struct device *dev = &pdev->dev; 696 struct plat_serial8250_port *p = dev->platform_data; 697 698 /* Don't map zero-based physical address */ 699 if (p->mapbase == 0) { 700 dev_warn(dev, "no physical address for uart#%d," 701 " so skipping early_init...\n", i); 702 continue; 703 } 704 /* 705 * Module 4KB + L4 interconnect 4KB 706 * Static mapping, never released 707 */ 708 p->membase = ioremap(p->mapbase, SZ_8K); 709 if (!p->membase) { 710 dev_err(dev, "ioremap failed for uart%i\n", i + 1); 711 continue; 712 } 713 714 sprintf(name, "uart%d_ick", i + 1); 715 uart->ick = clk_get(NULL, name); 716 if (IS_ERR(uart->ick)) { 717 dev_err(dev, "Could not get uart%d_ick\n", i + 1); 718 uart->ick = NULL; 719 } 720 721 sprintf(name, "uart%d_fck", i+1); 722 uart->fck = clk_get(NULL, name); 723 if (IS_ERR(uart->fck)) { 724 dev_err(dev, "Could not get uart%d_fck\n", i + 1); 725 uart->fck = NULL; 726 } 727 728 if (!cpu_is_omap44xx()) { 729 if (!uart->ick || !uart->fck) 730 continue; 731 } 732 733 uart->num = i; 734 p->private_data = uart; 735 uart->p = p; 736 737 if (cpu_is_omap44xx()) 738 p->irq += 32; 739 } 740} 741 742/** 743 * omap_serial_init_port() - initialize single serial port 744 * @port: serial port number (0-3) 745 * 746 * This function initialies serial driver for given @port only. 747 * Platforms can call this function instead of omap_serial_init() 748 * if they don't plan to use all available UARTs as serial ports. 749 * 750 * Don't mix calls to omap_serial_init_port() and omap_serial_init(), 751 * use only one of the two. 752 */ 753void __init omap_serial_init_port(int port) 754{ 755 struct omap_uart_state *uart; 756 struct platform_device *pdev; 757 struct device *dev; 758 759 BUG_ON(port < 0); 760 BUG_ON(port >= ARRAY_SIZE(omap_uart)); 761 762 uart = &omap_uart[port]; 763 pdev = &uart->pdev; 764 dev = &pdev->dev; 765 766 /* Don't proceed if there's no clocks available */ 767 if (unlikely(!uart->ick || !uart->fck)) { 768 WARN(1, "%s: can't init uart%d, no clocks available\n", 769 kobject_name(&dev->kobj), port); 770 return; 771 } 772 773 omap_uart_enable_clocks(uart); 774 775 omap_uart_reset(uart); 776 omap_uart_idle_init(uart); 777 778 list_add_tail(&uart->node, &uart_list); 779 780 if (WARN_ON(platform_device_register(pdev))) 781 return; 782 783 if ((cpu_is_omap34xx() && uart->padconf) || 784 (uart->wk_en && uart->wk_mask)) { 785 device_init_wakeup(dev, true); 786 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); 787 } 788 789 /* 790 * omap44xx: Never read empty UART fifo 791 * omap3xxx: Never read empty UART fifo on UARTs 792 * with IP rev >=0x52 793 */ 794 if (cpu_is_omap44xx()) 795 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; 796 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) 797 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) 798 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; 799 800 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { 801 uart->p->serial_in = serial_in_override; 802 uart->p->serial_out = serial_out_override; 803 } 804 805 /* Enable the MDR1 errata for OMAP3 */ 806 if (cpu_is_omap34xx()) 807 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; 808} 809 810/** 811 * omap_serial_init() - intialize all supported serial ports 812 * 813 * Initializes all available UARTs as serial ports. Platforms 814 * can call this function when they want to have default behaviour 815 * for serial ports (e.g initialize them all as serial ports). 816 */ 817void __init omap_serial_init(void) 818{ 819 int i, nr_ports; 820 821 if (!(cpu_is_omap3630() || cpu_is_omap4430())) 822 nr_ports = 3; 823 else 824 nr_ports = ARRAY_SIZE(omap_uart); 825 826 for (i = 0; i < nr_ports; i++) 827 omap_serial_init_port(i); 828} 829