/netbsd-current/sys/arch/mips/mips/ |
H A D | cache_tx39.c | 70 tx3900_icache_sync_range_16(register_t va, vsize_t size) argument 72 vaddr_t eva = round_line(va + size); 74 va = trunc_line(va); 76 if ((eva - va) >= mips_cache_info.mci_picache_size) { 78 va = MIPS_PHYS_TO_KSEG0(0); 82 tx3900_icache_do_inv_index_16(va, eva); 96 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 97 vaddr_t eva = va + mips_cache_info.mci_pdcache_size; 106 while (va < ev 120 tx3900_pdcache_inv_range_4(register_t va, vsize_t size) argument 139 tx3900_pdcache_wb_range_4(register_t va, vsize_t size) argument 164 tx3920_icache_sync_range_16wt(register_t va, vsize_t size) argument 174 tx3920_icache_sync_range_16wb(register_t va, vsize_t size) argument 190 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 208 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 224 tx3920_pdcache_wbinv_range_16wb(register_t va, vsize_t size) argument 243 tx3920_pdcache_inv_range_16(register_t va, vsize_t size) argument 262 tx3920_pdcache_wb_range_16wt(register_t va, vsize_t size) argument 269 tx3920_pdcache_wb_range_16wb(register_t va, vsize_t size) argument [all...] |
H A D | cache_r10k.c | 86 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 87 vaddr_t eva = va + mci->mci_picache_way_size; 93 while (va < eva) { 94 cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); 95 va++; 96 cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); 97 va += 63; 102 r10k_icache_sync_range(register_t va, vsize_t size) argument 104 vaddr_t eva = round_line(va + size); 106 va 119 r10k_icache_sync_range_index(vaddr_t va, vsize_t size) argument 162 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 174 r10k_pdcache_wbinv_range(register_t va, vsize_t size) argument 187 r10k_pdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 212 r10k_pdcache_inv_range(register_t va, vsize_t size) argument 225 r10k_pdcache_wb_range(register_t va, vsize_t size) argument 248 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 261 r10k_sdcache_wbinv_range(register_t va, vsize_t size) argument 276 r10k_sdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 302 r10k_sdcache_inv_range(register_t va, vsize_t size) argument 317 r10k_sdcache_wb_range(register_t va, vsize_t size) argument [all...] |
H A D | cache_ls2.c | 56 ls2_icache_sync_range(register_t va, vsize_t size) argument 59 const vaddr_t eva = round_line(va + size); 61 va = trunc_line(va); 63 if (va + mci->mci_picache_size <= eva) { 68 for (; va + 8 * 32 <= eva; va += 8 * 32) { 69 cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV); 70 cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV); 73 for (; va < ev 82 ls2_icache_sync_range_index(vaddr_t va, vsize_t size) argument 124 ls2_pdcache_inv_range(register_t va, vsize_t size) argument 142 ls2_pdcache_wbinv_range(register_t va, vsize_t size) argument 160 ls2_pdcache_wb_range(register_t va, vsize_t size) argument 169 ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 218 ls2_sdcache_inv_range(register_t va, vsize_t size) argument 238 ls2_sdcache_wbinv_range(register_t va, vsize_t size) argument 258 ls2_sdcache_wb_range(register_t va, vsize_t size) argument 267 ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument [all...] |
H A D | cache_r5k.c | 106 r5k_picache_sync_range(register_t va, vsize_t size) argument 109 mips_intern_dcache_sync_range(va, size); 110 mips_intern_icache_sync_range(va, size); 114 r5k_picache_sync_range_index(vaddr_t va, vsize_t size) argument 129 va = MIPS_PHYS_TO_KSEG0(va & way_mask); 131 eva = round_line(va + size, line_size); 132 va = trunc_line(va, line_size); 133 size = eva - va; 166 r5k_pdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 209 r4600v1_pdcache_wbinv_range_32(register_t va, vsize_t size) argument 244 r4600v2_pdcache_wbinv_range_32(register_t va, vsize_t size) argument 269 vr4131v1_pdcache_wbinv_range_16(register_t va, vsize_t size) argument 288 r4600v1_pdcache_inv_range_32(register_t va, vsize_t size) argument 314 r4600v2_pdcache_inv_range_32(register_t va, vsize_t size) argument 344 r4600v1_pdcache_wb_range_32(register_t va, vsize_t size) argument 370 r4600v2_pdcache_wb_range_32(register_t va, vsize_t size) argument 418 r5k_sdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 432 r5k_sdcache_wbinv_range(register_t va, vsize_t size) argument [all...] |
H A D | cache_r3k.c | 61 vaddr_t va = MIPS_PHYS_TO_KSEG0(0); local 62 vaddr_t eva = va + mips_cache_info.mci_picache_size; 64 r3k_picache_do_inv(va, eva); 68 r3k_icache_sync_range(register_t va, vsize_t size) argument 70 vaddr_t eva = round_line(va + size); 72 va = trunc_line(va); 74 if ((eva - va) >= mips_cache_info.mci_picache_size) { 79 r3k_picache_do_inv(va, eva); 85 vaddr_t va local 94 r3k_pdcache_inv_range(register_t va, vsize_t size) argument 109 r3k_pdcache_wb_range(register_t va, vsize_t size) argument [all...] |
H A D | cache_r4k.c | 67 r4k_icache_sync_range_generic(register_t va, vsize_t size) argument 69 mips_dcache_wb_range(va, size); 71 mips_intern_icache_sync_range_index(va, size); 75 r4k_icache_sync_range_index_generic(vaddr_t va, vsize_t size) argument 77 mips_dcache_wbinv_range_index(va, size); 85 va = MIPS_PHYS_TO_KSEG0(va & mips_cache_info.mci_picache_way_mask); 88 mips_intern_icache_sync_range_index(va, size);
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H A D | cache_mipsNN.c | 101 mipsNN_picache_sync_range(register_t va, vsize_t size) argument 104 mips_intern_dcache_sync_range(va, size); 105 mips_intern_icache_sync_range(va, size); 109 mipsNN_picache_sync_range_index(vaddr_t va, vsize_t size) argument 124 va = MIPS_PHYS_TO_KSEG0(va & way_mask); 126 eva = round_line(va + size, line_size); 127 va = trunc_line(va, line_size); 128 size = eva - va; 148 mipsNN_pdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument 191 mipsNN_sdcache_wbinv_range_index(vaddr_t va, vsize_t size) argument [all...] |
/netbsd-current/sys/arch/powerpc/booke/ |
H A D | booke_cache.c | 47 dcbf(vaddr_t va, vsize_t off) argument 49 __asm volatile("dcbf\t%0,%1" : : "b" (va), "r" (off)); 53 dcbst(vaddr_t va, vsize_t off) argument 55 __asm volatile("dcbst\t%0,%1" : : "b" (va), "r" (off)); 59 dcbi(vaddr_t va, vsize_t off) argument 61 __asm volatile("dcbi\t%0,%1" : : "b" (va), "r" (off)); 65 dcbz(vaddr_t va, vsize_t off) argument 67 __asm volatile("dcbz\t%0,%1" : : "b" (va), "r" (off)); 71 dcba(vaddr_t va, vsize_t off) argument 73 __asm volatile("dcba\t%0,%1" : : "b" (va), " 77 icbi(vaddr_t va, vsize_t off) argument 83 cache_op(vaddr_t va, vsize_t len, vsize_t line_size, enum cache_op op) argument 109 dcache_wb_page(vaddr_t va) argument 115 dcache_wbinv_page(vaddr_t va) argument 121 dcache_inv_page(vaddr_t va) argument 127 dcache_zero_page(vaddr_t va) argument 133 icache_inv_page(vaddr_t va) argument 142 dcache_wb(vaddr_t va, vsize_t len) argument 148 dcache_wbinv(vaddr_t va, vsize_t len) argument 154 dcache_inv(vaddr_t va, vsize_t len) argument 160 icache_inv(vaddr_t va, vsize_t len) argument [all...] |
/netbsd-current/sys/arch/cobalt/stand/boot/ |
H A D | cache.c | 52 pdcache_inv(uint32_t va, u_int size) argument 56 eva = round_line(va + size); 57 va = trunc_line(va); 59 while (va < eva) { 60 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV); 61 va += CACHELINESIZE; 66 pdcache_wb(uint32_t va, u_int size) argument 70 eva = round_line(va + size); 71 va 80 pdcache_wbinv(uint32_t va, u_int size) argument [all...] |
/netbsd-current/sys/arch/vax/include/ |
H A D | pte.h | 75 #define kvtopte(va) kvtopte0((vaddr_t) (va)) 77 kvtopte0(vaddr_t va) argument 85 : "g"(va), "o"(*Sysmap)); 91 : "g"(va)); 96 #define kvtophys(va) kvtophys0((vaddr_t) (va)) 98 kvtophys0(vaddr_t va) argument 107 : "g"(va), "o"(*Sysmap) : "cc"); 114 : "g"(va) [all...] |
/netbsd-current/lib/libc/sys/ |
H A D | vadvise.c | 35 int vadvise(int va); 38 vadvise(int va) argument 40 __USE(va);
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/netbsd-current/sys/arch/sparc/stand/common/ |
H A D | dvma.c | 51 #define getsegmap(va) (lduha(va, ASI_SEGMAP)) 52 #define setsegmap(va, pmeg) do stha(va, ASI_SEGMAP, pmeg); while(0) 84 int va = (int)addr; local 86 va -= base_va; 90 if (va < 0 || va >= DVMA_MAPLEN) 91 panic("dvma_mapin: va %x (DMA base %x)", va 105 int va = (int)addr; local [all...] |
/netbsd-current/sys/rump/librump/rumpvfs/ |
H A D | rumpvfs_compat50.c | 86 rump_vattr50_to_vattr(const struct vattr *_va50, struct vattr *va) argument 90 va->va_type = va50->va_type; 91 va->va_mode = va50->va_mode; 92 va->va_nlink = va50->va_nlink; 93 va->va_uid = va50->va_uid; 94 va->va_gid = va50->va_gid; 95 va->va_fsid = (long)va50->va_fsid; 96 va->va_fileid = va50->va_fileid; 97 va->va_size = va50->va_size; 98 va 112 rump_vattr_to_vattr50(const struct vattr *va, struct vattr *_va50) argument [all...] |
/netbsd-current/sys/arch/sh3/sh3/ |
H A D | cache_sh4.c | 204 cache_sh4_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits) argument 208 cca = base | (va & mask); 218 cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits) argument 221 (base | (va & mask)); 236 vaddr_t va = 0; local 243 while (va < eva) { 244 cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V); 245 va += 32 * 8; 252 sh4_icache_sync_range(vaddr_t va, vsize_t sz) argument 255 vaddr_t eva = round_line(va 272 sh4_icache_sync_range_index(vaddr_t va, vsize_t sz) argument 297 vaddr_t va = 0; local 311 sh4_dcache_wbinv_range(vaddr_t va, vsize_t sz) argument 323 sh4_dcache_wbinv_range_index(vaddr_t va, vsize_t sz) argument 345 sh4_dcache_inv_range(vaddr_t va, vsize_t sz) argument 357 sh4_dcache_wb_range(vaddr_t va, vsize_t sz) argument 377 cache_sh4_emode_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits, uint32_t way_shift) argument 399 cache_sh4_emode_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits, uint32_t way_shift) argument 432 vaddr_t va = 0; local 448 sh4_emode_icache_sync_range_index(vaddr_t va, vsize_t sz) argument 474 vaddr_t va = 0; local 485 sh4_emode_dcache_wbinv_range_index(vaddr_t va, vsize_t sz) argument [all...] |
H A D | cache_sh3.c | 142 cache_sh3_op_line_16_nway(int n, vaddr_t va, uint32_t bits) argument 148 va &= sh_cache_entry_mask; 152 cca = (SH3_CCA | way << sh_cache_way_shift | va); 164 cache_sh3_op_8lines_16_nway(int n, vaddr_t va, uint32_t bits) argument 170 va &= sh_cache_entry_mask; 175 (SH3_CCA | way << sh_cache_way_shift | va); 190 vaddr_t va; local 192 for (va = 0; va < sh_cache_way_size; va 197 sh3_cache_wbinv_range_index(vaddr_t va, vsize_t sz) argument 215 sh3_cache_wbinv_range(vaddr_t va, vsize_t sz) argument 236 sh3_cache_panic(vaddr_t va, vsize_t size) argument 243 sh3_cache_nop(vaddr_t va, vsize_t sz) argument [all...] |
/netbsd-current/sys/arch/hpcmips/vr/ |
H A D | ite8181_vrip.c | 65 struct vrip_attach_args *va = aux; local 69 if (va->va_addr == VRIPIFCF_ADDR_DEFAULT) 77 if (bus_space_map(va->va_iot, va->va_addr, va->va_size, 0, &ioh)) { 81 res = ite8181_probe(va->va_iot, ioh); 82 bus_space_unmap(va->va_iot, ioh, va->va_size); 93 struct vrip_attach_args *va = aux; local 96 sc->sc_baseaddr = va [all...] |
/netbsd-current/sys/arch/ia64/stand/efi/libefi/ |
H A D | copy.c | 41 efi_copyin(void *src, vaddr_t va, size_t len) argument 44 memcpy((void *)efimd_va2pa(va), src, len); 49 efi_copyout(vaddr_t va, void *dst, size_t len) argument 52 memcpy(dst, (void *)efimd_va2pa(va), len); 57 efi_readin(int fd, vaddr_t va, size_t len) argument 60 return (read(fd, (void *)efimd_va2pa(va), len));
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/netbsd-current/sys/arch/atari/vme/ |
H A D | vme.c | 82 struct vme_attach_args *va = aux; local 84 if (va->va_iosize) 85 aprint_normal(" port 0x%x", va->va_iobase); 86 if (va->va_iosize > 1) 87 aprint_normal("-0x%x", va->va_iobase + va->va_iosize - 1); 88 if (va->va_msize) 89 aprint_normal(" iomem 0x%x", va->va_maddr); 90 if (va->va_msize > 1) 91 aprint_normal("-0x%x", va 101 struct vme_attach_args va; local [all...] |
/netbsd-current/sys/arch/sun3/sun3/ |
H A D | control.c | 53 get_pte(vaddr_t va) argument 55 return (get_control_word(CONTROL_ADDR_BUILD(PGMAP_BASE, va))); 59 set_pte(vaddr_t va, u_int pte) argument 61 set_control_word(CONTROL_ADDR_BUILD(PGMAP_BASE, va), pte); 65 get_segmap(vaddr_t va) argument 67 return (get_control_byte(CONTROL_ADDR_BUILD(SEGMAP_BASE, va))); 71 set_segmap(vaddr_t va, int sme) argument 73 set_control_byte(CONTROL_ADDR_BUILD(SEGMAP_BASE, va), sme);
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H A D | cache.c | 66 char *va, *endva; local 79 va = (char *) pgva; 84 __asm volatile ("movsl %0, %1@" : : "d" (data), "a" (va)); 85 va += VAC_FLUSH_INCR; 86 } while (va < endva); 95 char *va, *endva; local 108 va = (char *) sgva; 113 __asm volatile ("movsl %0, %1@" : : "d" (data), "a" (va)); 114 va += VAC_FLUSH_INCR; 115 } while (va < endv 124 char *va, *endva; local 150 char *va, *endva; local [all...] |
/netbsd-current/sys/arch/mips/include/ |
H A D | cache_ls2.h | 51 #define cache_op_ls2_8line_4way(va, op) \ 72 : "r" (va), "i" (op) \ 75 #define cache_op_ls2_line_4way(va, op) \ 82 : "r" (va), "i" (op) \ 85 #define cache_op_ls2_8line(va, op) \ 94 : "r" (va), "i" (op) \ 97 #define cache_op_ls2_line(va, op) \ 103 : "r" (va), "i" (op) \
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/netbsd-current/sys/arch/sun68k/stand/libsa/ |
H A D | sun3.c | 105 u_int i, pa, pte, pgva, va; local 122 va = pgva = sun3_devmap; 130 va += (physaddr & PGOFSET); 134 printf("dev3_mapin: va=0x%x pte=0x%x\n", 135 va, sun3_get_pte(va)); 137 return ((char*)va); 183 int va = (int)addr; local 186 if ((va < SA_MIN_VA) || (va > 199 int va = (int)addr; local 226 sun3_get_pte(vaddr_t va) argument 234 sun3_set_pte(vaddr_t va, u_int pte) argument 241 sun3_get_segmap(vaddr_t va) argument 248 sun3_set_segmap(vaddr_t va, int sme) argument [all...] |
/netbsd-current/sys/rump/kern/lib/libsljit/arch/aarch64/ |
H A D | cpufunc.c | 44 aarch64_icache_sync_range(vaddr_t va, vsize_t sz) argument 48 // (void)rumpcomp_sync_icache((void *)va, (uint64_t)sz); 50 __builtin___clear_cache((void *)va, (char *)va + sz);
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/netbsd-current/sys/arch/evbppc/evbppc/ |
H A D | evbppc_machdep.c | 107 vaddr_t taddr, va; local 127 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 129 if (va == 0) 139 return (void *)(va + off); 143 unmapiodev(vaddr_t va, vsize_t sz) argument 146 if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) 149 sz = round_page((va & PAGE_MASK) + sz); 150 va = trunc_page(va); [all...] |
/netbsd-current/sys/arch/sh3/include/ |
H A D | mmu.h | 84 #define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 87 #define sh_tlb_update(a, va, pte) (*__sh_tlb_update)(a, va, pte) 92 #define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 95 #define sh_tlb_update(a, va, pte) sh3_tlb_update(a, va, pte) 100 #define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) [all...] |