1/*	$NetBSD: cache_ls2.h,v 1.4 2020/07/26 08:08:41 simonb Exp $	*/
2
3/*-
4 * Copyright (c) 2009 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas <matt@3am-software.com>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _MIPS_CACHE_LS2_H_
33#define	_MIPS_CACHE_LS2_H_
34
35/*
36 * Cache definitions/operations for Loongson-style caches.
37 */
38#define	CACHEOP_LS2_I_INDEX_INV		0
39#define	CACHEOP_LS2_D_INDEX_WB_INV	1
40#define	CACHEOP_LS2_S_INDEX_WB_INV	3
41#define	CACHEOP_LS2_D_HIT_INV		17
42#define	CACHEOP_LS2_S_HIT_INV		19
43#define	CACHEOP_LS2_D_HIT_WB_INV	21
44#define	CACHEOP_LS2_S_HIT_WB_INV	23
45
46#if !defined(_LOCORE)
47/*
48 * The way is encoded in the bottom 2 bits of VA.
49 */
50
51#define	cache_op_ls2_8line_4way(va, op)					\
52	__asm volatile(							\
53                ".set noreorder					\n\t"	\
54                "cache %1, 0x00(%0); cache %1, 0x20(%0)		\n\t"	\
55                "cache %1, 0x40(%0); cache %1, 0x60(%0)		\n\t"	\
56                "cache %1, 0x80(%0); cache %1, 0xa0(%0)		\n\t"	\
57                "cache %1, 0xc0(%0); cache %1, 0xe0(%0)		\n\t"	\
58                "cache %1, 0x01(%0); cache %1, 0x21(%0)		\n\t"	\
59                "cache %1, 0x41(%0); cache %1, 0x61(%0)		\n\t"	\
60                "cache %1, 0x81(%0); cache %1, 0xa1(%0)		\n\t"	\
61                "cache %1, 0xc1(%0); cache %1, 0xe1(%0)		\n\t"	\
62                "cache %1, 0x02(%0); cache %1, 0x22(%0)		\n\t"	\
63                "cache %1, 0x42(%0); cache %1, 0x62(%0)		\n\t"	\
64                "cache %1, 0x82(%0); cache %1, 0xa2(%0)		\n\t"	\
65                "cache %1, 0xc2(%0); cache %1, 0xe2(%0)		\n\t"	\
66                "cache %1, 0x03(%0); cache %1, 0x23(%0)		\n\t"	\
67                "cache %1, 0x43(%0); cache %1, 0x63(%0)		\n\t"	\
68                "cache %1, 0x83(%0); cache %1, 0xa3(%0)		\n\t"	\
69                "cache %1, 0xc3(%0); cache %1, 0xe3(%0)		\n\t"	\
70                ".set reorder"						\
71            :								\
72            : "r" (va), "i" (op)					\
73            : "memory");
74
75#define	cache_op_ls2_line_4way(va, op)					\
76	__asm volatile(							\
77                ".set noreorder					\n\t"	\
78                "cache %1, 0(%0); cache %1, 1(%0)		\n\t"	\
79                "cache %1, 2(%0); cache %1, 3(%0)		\n\t"	\
80                ".set reorder"						\
81            :								\
82            : "r" (va), "i" (op)					\
83            : "memory");
84
85#define	cache_op_ls2_8line(va, op)					\
86	__asm volatile(							\
87                ".set noreorder					\n\t"	\
88                "cache %1, 0x00(%0); cache %1, 0x20(%0)		\n\t"	\
89                "cache %1, 0x40(%0); cache %1, 0x60(%0)		\n\t"	\
90                "cache %1, 0x80(%0); cache %1, 0xa0(%0)		\n\t"	\
91                "cache %1, 0xc0(%0); cache %1, 0xe0(%0)		\n\t"	\
92                ".set reorder"						\
93            :								\
94            : "r" (va), "i" (op)					\
95            : "memory");
96
97#define	cache_op_ls2_line(va, op)					\
98	__asm volatile(							\
99                ".set noreorder					\n\t"	\
100                "cache %1, 0(%0)				\n\t"	\
101                ".set reorder"						\
102            :								\
103            : "r" (va), "i" (op)					\
104            : "memory");
105
106void	ls2_icache_sync_all(void);
107void	ls2_icache_sync_range(register_t, vsize_t);
108void	ls2_icache_sync_range_index(vaddr_t, vsize_t);
109
110void	ls2_pdcache_wbinv_all(void);
111void	ls2_pdcache_wbinv_range(register_t, vsize_t);
112void	ls2_pdcache_wbinv_range_index(vaddr_t, vsize_t);
113
114void	ls2_pdcache_inv_range(register_t, vsize_t);
115void	ls2_pdcache_wb_range(register_t, vsize_t);
116
117void	ls2_sdcache_wbinv_all(void);
118void	ls2_sdcache_wbinv_range(register_t, vsize_t);
119void	ls2_sdcache_wbinv_range_index(vaddr_t, vsize_t);
120
121void	ls2_sdcache_inv_range(register_t, vsize_t);
122void	ls2_sdcache_wb_range(register_t, vsize_t);
123
124#endif /* !_LOCORE */
125#endif /* !_MIPS_CACHE_LS2_H_ */
126