1/* $NetBSD: mmu.h,v 1.11 2022/02/23 21:54:40 andvar Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _SH3_MMU_H_ 33#define _SH3_MMU_H_ 34 35/* 36 * Initialize routines. 37 * sh_mmu_init Assign function vector. Don't access hardware. 38 * Call as early as possible. 39 * sh_mmu_start Reset TLB entry, set default ASID, and start to 40 * translate addresses. 41 * Call after exception vector was installed. 42 * 43 * TLB access ops. 44 * sh_tlb_invalidate_addr invalidate TLB entries for given 45 * virtual addr with ASID. 46 * sh_tlb_invalidate_asid invalidate TLB entries for given ASID. 47 * sh_tlb_invalidate_all invalidate all non-wired TLB entries. 48 * sh_tlb_set_asid set ASID. 49 * sh_tlb_update load new PTE to TLB. 50 * 51 */ 52 53void sh_mmu_init(void); 54void sh_mmu_information(void); 55void sh_tlb_set_asid(int); 56 57#ifdef SH3 58void sh3_mmu_start(void); 59void sh3_tlb_invalidate_addr(int, vaddr_t); 60void sh3_tlb_invalidate_asid(int); 61void sh3_tlb_invalidate_all(void); 62void sh3_tlb_update(int, vaddr_t, uint32_t); 63#endif 64 65#ifdef SH4 66void sh4_mmu_start(void); 67void sh4_tlb_invalidate_addr(int, vaddr_t); 68void sh4_tlb_invalidate_asid(int); 69void sh4_tlb_invalidate_all(void); 70void sh4_tlb_update(int, vaddr_t, uint32_t); 71#endif 72 73 74#if defined(SH3) && defined(SH4) 75extern uint32_t __sh_PTEH; 76 77extern void (*__sh_mmu_start)(void); 78extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t); 79extern void (*__sh_tlb_invalidate_asid)(int); 80extern void (*__sh_tlb_invalidate_all)(void); 81extern void (*__sh_tlb_update)(int, vaddr_t, uint32_t); 82 83#define sh_mmu_start() (*__sh_mmu_start)() 84#define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 85#define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a) 86#define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)() 87#define sh_tlb_update(a, va, pte) (*__sh_tlb_update)(a, va, pte) 88 89#elif defined(SH3) 90 91#define sh_mmu_start() sh3_mmu_start() 92#define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 93#define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a) 94#define sh_tlb_invalidate_all() sh3_tlb_invalidate_all() 95#define sh_tlb_update(a, va, pte) sh3_tlb_update(a, va, pte) 96 97#elif defined(SH4) 98 99#define sh_mmu_start() sh4_mmu_start() 100#define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) 101#define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a) 102#define sh_tlb_invalidate_all() sh4_tlb_invalidate_all() 103#define sh_tlb_update(a, va, pte) sh4_tlb_update(a, va, pte) 104 105#endif 106 107#endif /* !_SH3_MMU_H_ */ 108