/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/modules/stats/ |
H A D | stats.c | 120 unsigned int reg_data; local 136 ®_data, sizeof(unsigned int), &flag)) 137 core_stats->enabled = reg_data; 143 ®_data, sizeof(unsigned int), &flag)) { 144 if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX) 147 core_stats->entries = reg_data;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_vcn_v1_0.c | 638 uint32_t reg_data = 0; local 642 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 644 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 645 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 646 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 653 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 655 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 657 reg_data | 1212 uint32_t reg_data = 0; local [all...] |
H A D | amdgpu_vcn_v2_0.c | 559 uint32_t reg_data = 0; local 563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 566 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 567 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 568 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 1143 uint32_t reg_data = 0; local 1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1160 reg_data | [all...] |
H A D | amdgpu_vcn_v2_5.c | 650 uint32_t reg_data = 0; local 654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 657 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 658 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 659 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 1373 uint32_t reg_data = 0; local 1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) & 1390 reg_data | [all...] |
H A D | amdgpu_atombios.c | 1601 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = local 1622 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1624 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1628 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1633 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1642 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1643 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1645 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
H A D | kfd_pm4_headers_diq.h | 201 unsigned int reg_data[1]; /*1..N of these fields */ member in struct:pm4__set_config_reg
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H A D | kfd_dbgdev.c | 435 packets_vec[0].reg_data[0] = cntl.u32All; 445 packets_vec[1].reg_data[0] = addrHi.u32All; 455 packets_vec[2].reg_data[0] = addrLo.u32All; 471 packets_vec[3].reg_data[0] = cntl.u32All; 661 packets_vec[0].reg_data[0] = reg_gfx_index.u32All; 670 packets_vec[1].reg_data[0] = reg_sq_cmd.u32All; 685 packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
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/netbsd-current/external/gpl3/gdb.old/dist/gdb/ |
H A D | arm-linux-tdep.c | 553 const gdb_byte *reg_data; local 557 reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE; 564 memcpy (buf, reg_data, 4); 567 memcpy (buf, reg_data + 4, 4); 568 memcpy (buf + 4, reg_data, 4); 573 memcpy (buf, reg_data, 4); 574 memcpy (buf + 4, reg_data + 8, 4); 575 memcpy (buf + 8, reg_data + 4, 4); 588 gdb_byte *reg_data; local 599 reg_data [all...] |
/netbsd-current/external/gpl3/gdb/dist/gdb/ |
H A D | arm-linux-tdep.c | 554 const gdb_byte *reg_data; local 558 reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE; 565 memcpy (buf, reg_data, 4); 568 memcpy (buf, reg_data + 4, 4); 569 memcpy (buf + 4, reg_data, 4); 574 memcpy (buf, reg_data, 4); 575 memcpy (buf + 4, reg_data + 8, 4); 576 memcpy (buf + 8, reg_data + 4, 4); 589 gdb_byte *reg_data; local 600 reg_data [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
H A D | amdgpu_dce110_compressor.c | 253 uint32_t reg_data; local 255 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); 256 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 257 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
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H A D | amdgpu_dce110_transform_v.c | 641 uint32_t reg_data = 0; local 666 reg_data, 672 reg_data, 677 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
H A D | edid.c | 297 u32 reg_data = 0; local 310 reg_data |= (byte_data << (i << 3)); 313 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count); local
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
H A D | amdgpu_dce112_compressor.c | 428 uint32_t reg_data; local 430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); 431 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | amdgpu_smu8_smumgr.c | 183 uint32_t reg_data; local 213 reg_data = lower_32_bits(info.mc_addr) & 215 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data); 217 reg_data = upper_32_bits(info.mc_addr) & 219 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
H A D | amdgpu_dce_audio.c | 64 uint32_t reg_data) 74 AZALIA_ENDPOINT_REG_DATA, reg_data); 77 reg_index, reg_data); 62 write_indirect_azalia_reg(struct audio *audio, uint32_t reg_index, uint32_t reg_data) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | amdgpu_ppatomctrl.c | 59 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) local 64 while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK && 66 tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); 70 (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >> 77 (uint32_t)*((uint32_t *)reg_data + j); 88 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 89 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; 92 PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),
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/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_atombios.c | 4007 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = local 4028 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4030 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4034 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4039 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4048 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4049 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4051 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
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/netbsd-current/sys/external/bsd/drm2/dist/drm/i915/ |
H A D | i915_perf.c | 1937 const struct i915_oa_reg *reg_data, 1950 *cs++ = i915_mmio_reg_offset(reg_data[i].addr); 1951 *cs++ = reg_data[i].value; 1936 write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32 n_regs) argument
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/netbsd-current/sys/dev/pci/ |
H A D | if_wm.c | 4997 uint16_t reg_data, reg_addr; local 4999 if (wm_nvm_read(sc, (word_addr + i * 2), 1, ®_data) != 0) 5006 phy_page = reg_data; 5013 reg_data);
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