Lines Matching refs:reg_data
650 uint32_t reg_data = 0;
654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
657 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
658 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
659 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1373 uint32_t reg_data = 0;
1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
1390 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1391 WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1421 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1422 WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);