Searched refs:mmVM_L2_CNTL4 (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfxhub_v1_0.c181 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
H A Damdgpu_gmc_v8_0.c889 tmp = RREG32(mmVM_L2_CNTL4);
902 WREG32(mmVM_L2_CNTL4, tmp);
H A Damdgpu_mmhub_v1_0.c200 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_d.h659 #define mmVM_L2_CNTL4 0x578 macro
H A Dgmc_8_1_d.h657 #define mmVM_L2_CNTL4 0x578 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_offset.h1310 #define mmVM_L2_CNTL4 0x0697 macro
H A Dmmhub_9_1_offset.h1342 #define mmVM_L2_CNTL4 0x0697 macro
H A Dmmhub_9_3_0_offset.h1326 #define mmVM_L2_CNTL4 0x0697 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1206 #define mmVM_L2_CNTL4 0x0857 macro
H A Dgc_9_1_offset.h1232 #define mmVM_L2_CNTL4 0x0857 macro
H A Dgc_9_2_1_offset.h1170 #define mmVM_L2_CNTL4 0x0857 macro

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