1/* $NetBSD: gmc_8_2_d.h,v 1.3 2021/12/18 23:45:15 riastradh Exp $ */ 2 3/* 4 * GMC_8_2 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef GMC_8_2_D_H 27#define GMC_8_2_D_H 28 29#define mmMC_CONFIG 0x800 30#define mmMC_ARB_ATOMIC 0x9be 31#define mmMC_ARB_AGE_CNTL 0x9bf 32#define mmMC_ARB_RET_CREDITS2 0x9c0 33#define mmMC_ARB_FED_CNTL 0x9c1 34#define mmMC_ARB_GECC2_STATUS 0x9c2 35#define mmMC_ARB_GECC2_MISC 0x9c3 36#define mmMC_ARB_GECC2_DEBUG 0x9c4 37#define mmMC_ARB_GECC2_DEBUG2 0x9c5 38#define mmMC_ARB_PERF_CID 0x9c6 39#define mmMC_ARB_SNOOP 0x9c7 40#define mmMC_ARB_GRUB 0x9c8 41#define mmMC_ARB_GECC2 0x9c9 42#define mmMC_ARB_GECC2_CLI 0x9ca 43#define mmMC_ARB_ADDR_SWIZ0 0x9cb 44#define mmMC_ARB_ADDR_SWIZ1 0x9cc 45#define mmMC_ARB_MISC3 0x9cd 46#define mmMC_ARB_GRUB_PROMOTE 0x9ce 47#define mmMC_ARB_RTT_DATA 0x9cf 48#define mmMC_ARB_RTT_CNTL0 0x9d0 49#define mmMC_ARB_RTT_CNTL1 0x9d1 50#define mmMC_ARB_RTT_CNTL2 0x9d2 51#define mmMC_ARB_RTT_DEBUG 0x9d3 52#define mmMC_ARB_CAC_CNTL 0x9d4 53#define mmMC_ARB_MISC2 0x9d5 54#define mmMC_ARB_MISC 0x9d6 55#define mmMC_ARB_BANKMAP 0x9d7 56#define mmMC_ARB_RAMCFG 0x9d8 57#define mmMC_ARB_POP 0x9d9 58#define mmMC_ARB_MINCLKS 0x9da 59#define mmMC_ARB_SQM_CNTL 0x9db 60#define mmMC_ARB_ADDR_HASH 0x9dc 61#define mmMC_ARB_DRAM_TIMING 0x9dd 62#define mmMC_ARB_DRAM_TIMING2 0x9de 63#define mmMC_ARB_WTM_CNTL_RD 0x9df 64#define mmMC_ARB_WTM_CNTL_WR 0x9e0 65#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 66#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 67#define mmMC_ARB_TM_CNTL_RD 0x9e3 68#define mmMC_ARB_TM_CNTL_WR 0x9e4 69#define mmMC_ARB_LAZY0_RD 0x9e5 70#define mmMC_ARB_LAZY0_WR 0x9e6 71#define mmMC_ARB_LAZY1_RD 0x9e7 72#define mmMC_ARB_LAZY1_WR 0x9e8 73#define mmMC_ARB_AGE_RD 0x9e9 74#define mmMC_ARB_AGE_WR 0x9ea 75#define mmMC_ARB_RFSH_CNTL 0x9eb 76#define mmMC_ARB_RFSH_RATE 0x9ec 77#define mmMC_ARB_PM_CNTL 0x9ed 78#define mmMC_ARB_GDEC_RD_CNTL 0x9ee 79#define mmMC_ARB_GDEC_WR_CNTL 0x9ef 80#define mmMC_ARB_LM_RD 0x9f0 81#define mmMC_ARB_LM_WR 0x9f1 82#define mmMC_ARB_REMREQ 0x9f2 83#define mmMC_ARB_REPLAY 0x9f3 84#define mmMC_ARB_RET_CREDITS_RD 0x9f4 85#define mmMC_ARB_RET_CREDITS_WR 0x9f5 86#define mmMC_ARB_MAX_LAT_CID 0x9f6 87#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 88#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 89#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9 90#define mmMC_ARB_CG 0x9fa 91#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb 92#define mmMC_ARB_DRAM_TIMING_1 0x9fc 93#define mmMC_ARB_BUSY_STATUS 0x9fd 94#define mmMC_ARB_DRAM_TIMING2_1 0x9ff 95#define mmMC_ARB_GRUB2 0xa01 96#define mmMC_ARB_BURST_TIME 0xa02 97#define mmMC_CITF_XTRA_ENABLE 0x96d 98#define mmCC_MC_MAX_CHANNEL 0x96e 99#define mmMC_CG_CONFIG 0x96f 100#define mmMC_CITF_CNTL 0x970 101#define mmMC_CITF_CREDITS_VM 0x971 102#define mmMC_CITF_CREDITS_ARB_RD 0x972 103#define mmMC_CITF_CREDITS_ARB_WR 0x973 104#define mmMC_CITF_DAGB_CNTL 0x974 105#define mmMC_CITF_INT_CREDITS 0x975 106#define mmMC_CITF_RET_MODE 0x976 107#define mmMC_CITF_DAGB_DLY 0x977 108#define mmMC_RD_GRP_EXT 0x978 109#define mmMC_WR_GRP_EXT 0x979 110#define mmMC_CITF_REMREQ 0x97a 111#define mmMC_WR_TC0 0x97b 112#define mmMC_WR_TC1 0x97c 113#define mmMC_CITF_INT_CREDITS_WR 0x97d 114#define mmMC_CITF_CREDITS_ARB_RD2 0x97e 115#define mmMC_CITF_WTM_RD_CNTL 0x97f 116#define mmMC_CITF_WTM_WR_CNTL 0x980 117#define mmMC_RD_CB 0x981 118#define mmMC_RD_DB 0x982 119#define mmMC_RD_TC0 0x983 120#define mmMC_RD_TC1 0x984 121#define mmMC_RD_HUB 0x985 122#define mmMC_WR_CB 0x986 123#define mmMC_WR_DB 0x987 124#define mmMC_WR_HUB 0x988 125#define mmMC_CITF_CREDITS_XBAR 0x989 126#define mmMC_RD_GRP_LCL 0x98a 127#define mmMC_WR_GRP_LCL 0x98b 128#define mmMC_CITF_PERF_MON_CNTL2 0x98e 129#define mmMC_CITF_PERF_MON_RSLT2 0x991 130#define mmMC_CITF_MISC_RD_CG 0x992 131#define mmMC_CITF_MISC_WR_CG 0x993 132#define mmMC_CITF_MISC_VM_CG 0x994 133#define mmMC_HUB_MISC_POWER 0x82d 134#define mmMC_HUB_MISC_HUB_CG 0x82e 135#define mmMC_HUB_MISC_VM_CG 0x82f 136#define mmMC_HUB_MISC_SIP_CG 0x830 137#define mmMC_HUB_MISC_STATUS 0x832 138#define mmMC_HUB_MISC_OVERRIDE 0x833 139#define mmMC_HUB_MISC_FRAMING 0x834 140#define mmMC_HUB_WDP_CNTL 0x835 141#define mmMC_HUB_WDP_ERR 0x836 142#define mmMC_HUB_WDP_BP 0x837 143#define mmMC_HUB_WDP_STATUS 0x838 144#define mmMC_HUB_RDREQ_STATUS 0x839 145#define mmMC_HUB_WRRET_STATUS 0x83a 146#define mmMC_HUB_RDREQ_CNTL 0x83b 147#define mmMC_HUB_WRRET_CNTL 0x83c 148#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d 149#define mmMC_HUB_WDP_WTM_CNTL 0x83e 150#define mmMC_HUB_WDP_CREDITS 0x83f 151#define mmMC_HUB_WDP_CREDITS2 0x840 152#define mmMC_HUB_WDP_GBL0 0x841 153#define mmMC_HUB_WDP_GBL1 0x842 154#define mmMC_HUB_RDREQ_CREDITS 0x844 155#define mmMC_HUB_RDREQ_CREDITS2 0x845 156#define mmMC_HUB_SHARED_DAGB_DLY 0x846 157#define mmMC_HUB_MISC_IDLE_STATUS 0x847 158#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 159#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 160#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a 161#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b 162#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c 163#define mmMC_HUB_WDP_SH2 0x84d 164#define mmMC_HUB_WDP_SH3 0x84e 165#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f 166#define mmMC_HUB_RDREQ_MCDW 0x851 167#define mmMC_HUB_RDREQ_MCDX 0x852 168#define mmMC_HUB_RDREQ_MCDY 0x853 169#define mmMC_HUB_RDREQ_MCDZ 0x854 170#define mmMC_HUB_RDREQ_SIP 0x855 171#define mmMC_HUB_RDREQ_GBL0 0x856 172#define mmMC_HUB_RDREQ_GBL1 0x857 173#define mmMC_HUB_RDREQ_SMU 0x858 174#define mmMC_HUB_RDREQ_SDMA0 0x859 175#define mmMC_HUB_RDREQ_HDP 0x85a 176#define mmMC_HUB_RDREQ_SDMA1 0x85b 177#define mmMC_HUB_RDREQ_RLC 0x85c 178#define mmMC_HUB_RDREQ_SEM 0x85d 179#define mmMC_HUB_RDREQ_VCE0 0x85e 180#define mmMC_HUB_RDREQ_UMC 0x85f 181#define mmMC_HUB_RDREQ_UVD 0x860 182#define mmMC_HUB_RDREQ_DMIF 0x862 183#define mmMC_HUB_RDREQ_MCIF 0x863 184#define mmMC_HUB_RDREQ_VMC 0x864 185#define mmMC_HUB_RDREQ_VCEU0 0x865 186#define mmMC_HUB_WDP_MCDW 0x866 187#define mmMC_HUB_WDP_MCDX 0x867 188#define mmMC_HUB_WDP_MCDY 0x868 189#define mmMC_HUB_WDP_MCDZ 0x869 190#define mmMC_HUB_WDP_SIP 0x86a 191#define mmMC_HUB_WDP_SDMA1 0x86b 192#define mmMC_HUB_WDP_SH0 0x86c 193#define mmMC_HUB_WDP_MCIF 0x86d 194#define mmMC_HUB_WDP_VCE0 0x86e 195#define mmMC_HUB_WDP_XDP 0x86f 196#define mmMC_HUB_WDP_IH 0x870 197#define mmMC_HUB_WDP_RLC 0x871 198#define mmMC_HUB_WDP_SEM 0x872 199#define mmMC_HUB_WDP_SMU 0x873 200#define mmMC_HUB_WDP_SH1 0x874 201#define mmMC_HUB_WDP_UMC 0x875 202#define mmMC_HUB_WDP_UVD 0x876 203#define mmMC_HUB_WDP_HDP 0x877 204#define mmMC_HUB_WDP_SDMA0 0x878 205#define mmMC_HUB_WRRET_MCDW 0x879 206#define mmMC_HUB_WRRET_MCDX 0x87a 207#define mmMC_HUB_WRRET_MCDY 0x87b 208#define mmMC_HUB_WRRET_MCDZ 0x87c 209#define mmMC_HUB_WDP_VCEU0 0x87d 210#define mmMC_HUB_WDP_XDMAM 0x87e 211#define mmMC_HUB_WDP_XDMA 0x87f 212#define mmMC_HUB_RDREQ_XDMAM 0x880 213#define mmMC_HUB_RDREQ_ACPG 0x881 214#define mmMC_HUB_RDREQ_ACPO 0x882 215#define mmMC_HUB_RDREQ_SAMMSP 0x883 216#define mmMC_HUB_RDREQ_VP8 0x884 217#define mmMC_HUB_RDREQ_VP8U 0x885 218#define mmMC_HUB_WDP_ACPG 0x886 219#define mmMC_HUB_WDP_ACPO 0x887 220#define mmMC_HUB_WDP_SAMMSP 0x888 221#define mmMC_HUB_WDP_VP8 0x889 222#define mmMC_HUB_WDP_VP8U 0x88a 223#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 224#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 225#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 226#define mmMC_HUB_WDP_ISP_SPM 0xde3 227#define mmMC_HUB_WDP_ISP_MPS 0xde4 228#define mmMC_HUB_WDP_ISP_MPM 0xde5 229#define mmMC_HUB_WDP_ISP_CCPU 0xde6 230#define mmMC_HUB_RDREQ_MCDS 0xde7 231#define mmMC_HUB_RDREQ_MCDT 0xde8 232#define mmMC_HUB_RDREQ_MCDU 0xde9 233#define mmMC_HUB_RDREQ_MCDV 0xdea 234#define mmMC_HUB_WDP_MCDS 0xdeb 235#define mmMC_HUB_WDP_MCDT 0xdec 236#define mmMC_HUB_WDP_MCDU 0xded 237#define mmMC_HUB_WDP_MCDV 0xdee 238#define mmMC_HUB_WRRET_MCDS 0xdef 239#define mmMC_HUB_WRRET_MCDT 0xdf0 240#define mmMC_HUB_WRRET_MCDU 0xdf1 241#define mmMC_HUB_WRRET_MCDV 0xdf2 242#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 243#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 244#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 245#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 246#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 247#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 248#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 249#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa 250#define mmMC_HUB_WDP_BP2 0xdfb 251#define mmMC_HUB_RDREQ_VCE1 0xdfc 252#define mmMC_HUB_RDREQ_VCEU1 0xdfd 253#define mmMC_HUB_WDP_VCE1 0xdfe 254#define mmMC_HUB_WDP_VCEU1 0xdff 255#define mmMC_RPB_CONF 0x94d 256#define mmMC_RPB_IF_CONF 0x94e 257#define mmMC_RPB_DBG1 0x94f 258#define mmMC_RPB_EFF_CNTL 0x950 259#define mmMC_RPB_ARB_CNTL 0x951 260#define mmMC_RPB_BIF_CNTL 0x952 261#define mmMC_RPB_WR_SWITCH_CNTL 0x953 262#define mmMC_RPB_WR_COMBINE_CNTL 0x954 263#define mmMC_RPB_RD_SWITCH_CNTL 0x955 264#define mmMC_RPB_CID_QUEUE_WR 0x956 265#define mmMC_RPB_CID_QUEUE_RD 0x957 266#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 267#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 268#define mmMC_RPB_CID_QUEUE_EX 0x95a 269#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b 270#define mmMC_RPB_TCI_CNTL 0x95c 271#define mmMC_RPB_TCI_CNTL2 0x95d 272#define mmMC_SHARED_CHMAP 0x801 273#define mmMC_SHARED_CHREMAP 0x802 274#define mmMC_RD_GRP_GFX 0x803 275#define mmMC_WR_GRP_GFX 0x804 276#define mmMC_RD_GRP_SYS 0x805 277#define mmMC_WR_GRP_SYS 0x806 278#define mmMC_RD_GRP_OTH 0x807 279#define mmMC_WR_GRP_OTH 0x808 280#define mmMC_VM_FB_LOCATION 0x809 281#define mmMC_VM_AGP_TOP 0x80a 282#define mmMC_VM_AGP_BOT 0x80b 283#define mmMC_VM_AGP_BASE 0x80c 284#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d 285#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e 286#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f 287#define mmMC_VM_DC_WRITE_CNTL 0x810 288#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 289#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 290#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 291#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 292#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 293#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 294#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 295#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 296#define mmMC_VM_MX_L1_TLB_CNTL 0x819 297#define mmMC_VM_FB_OFFSET 0x81a 298#define mmMC_VM_STEERING 0x81b 299#define mmMC_SHARED_CHREMAP2 0x81c 300#define mmMC_SHARED_VF_ENABLE 0x81d 301#define mmMC_SHARED_VIRT_RESET_REQ 0x81e 302#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f 303#define mmMC_CONFIG_MCD 0x828 304#define mmMC_CG_CONFIG_MCD 0x829 305#define mmMC_MEM_POWER_LS 0x82a 306#define mmMC_SHARED_BLACKOUT_CNTL 0x82b 307#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 308#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892 309#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 310#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 311#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 312#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 313#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 314#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 315#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 316#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 317#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 318#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a 319#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b 320#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c 321#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d 322#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 323#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 324#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 325#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd 326#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce 327#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf 328#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 329#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 330#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 331#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 332#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 333#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 334#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 335#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 336#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 337#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 338#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da 339#define mmMC_XPB_RTR_DEST_MAP0 0x8db 340#define mmMC_XPB_RTR_DEST_MAP1 0x8dc 341#define mmMC_XPB_RTR_DEST_MAP2 0x8dd 342#define mmMC_XPB_RTR_DEST_MAP3 0x8de 343#define mmMC_XPB_RTR_DEST_MAP4 0x8df 344#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 345#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 346#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 347#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 348#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 349#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 350#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 351#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 352#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 353#define mmMC_XPB_CLG_CFG0 0x8e9 354#define mmMC_XPB_CLG_CFG1 0x8ea 355#define mmMC_XPB_CLG_CFG2 0x8eb 356#define mmMC_XPB_CLG_CFG3 0x8ec 357#define mmMC_XPB_CLG_CFG4 0x8ed 358#define mmMC_XPB_CLG_CFG5 0x8ee 359#define mmMC_XPB_CLG_CFG6 0x8ef 360#define mmMC_XPB_CLG_CFG7 0x8f0 361#define mmMC_XPB_CLG_CFG8 0x8f1 362#define mmMC_XPB_CLG_CFG9 0x8f2 363#define mmMC_XPB_CLG_CFG10 0x8f3 364#define mmMC_XPB_CLG_CFG11 0x8f4 365#define mmMC_XPB_CLG_CFG12 0x8f5 366#define mmMC_XPB_CLG_CFG13 0x8f6 367#define mmMC_XPB_CLG_CFG14 0x8f7 368#define mmMC_XPB_CLG_CFG15 0x8f8 369#define mmMC_XPB_CLG_CFG16 0x8f9 370#define mmMC_XPB_CLG_CFG17 0x8fa 371#define mmMC_XPB_CLG_CFG18 0x8fb 372#define mmMC_XPB_CLG_CFG19 0x8fc 373#define mmMC_XPB_CLG_EXTRA 0x8fd 374#define mmMC_XPB_LB_ADDR 0x8fe 375#define mmMC_XPB_UNC_THRESH_HST 0x8ff 376#define mmMC_XPB_UNC_THRESH_SID 0x900 377#define mmMC_XPB_WCB_STS 0x901 378#define mmMC_XPB_WCB_CFG 0x902 379#define mmMC_XPB_P2P_BAR_CFG 0x903 380#define mmMC_XPB_P2P_BAR0 0x904 381#define mmMC_XPB_P2P_BAR1 0x905 382#define mmMC_XPB_P2P_BAR2 0x906 383#define mmMC_XPB_P2P_BAR3 0x907 384#define mmMC_XPB_P2P_BAR4 0x908 385#define mmMC_XPB_P2P_BAR5 0x909 386#define mmMC_XPB_P2P_BAR6 0x90a 387#define mmMC_XPB_P2P_BAR7 0x90b 388#define mmMC_XPB_P2P_BAR_SETUP 0x90c 389#define mmMC_XPB_P2P_BAR_DEBUG 0x90d 390#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e 391#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f 392#define mmMC_XPB_PEER_SYS_BAR0 0x910 393#define mmMC_XPB_PEER_SYS_BAR1 0x911 394#define mmMC_XPB_PEER_SYS_BAR2 0x912 395#define mmMC_XPB_PEER_SYS_BAR3 0x913 396#define mmMC_XPB_PEER_SYS_BAR4 0x914 397#define mmMC_XPB_PEER_SYS_BAR5 0x915 398#define mmMC_XPB_PEER_SYS_BAR6 0x916 399#define mmMC_XPB_PEER_SYS_BAR7 0x917 400#define mmMC_XPB_PEER_SYS_BAR8 0x918 401#define mmMC_XPB_PEER_SYS_BAR9 0x919 402#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a 403#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b 404#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c 405#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d 406#define mmMC_XPB_CLK_GAT 0x91e 407#define mmMC_XPB_INTF_CFG 0x91f 408#define mmMC_XPB_INTF_STS 0x920 409#define mmMC_XPB_PIPE_STS 0x921 410#define mmMC_XPB_SUB_CTRL 0x922 411#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 412#define mmMC_XPB_PERF_KNOBS 0x924 413#define mmMC_XPB_STICKY 0x925 414#define mmMC_XPB_STICKY_W1C 0x926 415#define mmMC_XPB_MISC_CFG 0x927 416#define mmMC_XPB_CLG_CFG20 0x928 417#define mmMC_XPB_CLG_CFG21 0x929 418#define mmMC_XPB_CLG_CFG22 0x92a 419#define mmMC_XPB_CLG_CFG23 0x92b 420#define mmMC_XPB_CLG_CFG24 0x92c 421#define mmMC_XPB_CLG_CFG25 0x92d 422#define mmMC_XPB_CLG_CFG26 0x92e 423#define mmMC_XPB_CLG_CFG27 0x92f 424#define mmMC_XPB_CLG_CFG28 0x930 425#define mmMC_XPB_CLG_CFG29 0x931 426#define mmMC_XPB_CLG_CFG30 0x932 427#define mmMC_XPB_CLG_CFG31 0x933 428#define mmMC_XPB_INTF_CFG2 0x934 429#define mmMC_XPB_CLG_EXTRA_RD 0x935 430#define mmMC_XPB_CLG_CFG32 0x936 431#define mmMC_XPB_CLG_CFG33 0x937 432#define mmMC_XPB_CLG_CFG34 0x938 433#define mmMC_XPB_CLG_CFG35 0x939 434#define mmMC_XPB_CLG_CFG36 0x93a 435#define mmMC_XBAR_ADDR_DEC 0xc80 436#define mmMC_XBAR_REMOTE 0xc81 437#define mmMC_XBAR_WRREQ_CREDIT 0xc82 438#define mmMC_XBAR_RDREQ_CREDIT 0xc83 439#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 440#define mmMC_XBAR_WRRET_CREDIT1 0xc85 441#define mmMC_XBAR_WRRET_CREDIT2 0xc86 442#define mmMC_XBAR_RDRET_CREDIT1 0xc87 443#define mmMC_XBAR_RDRET_CREDIT2 0xc88 444#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 445#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a 446#define mmMC_XBAR_CHTRIREMAP 0xc8b 447#define mmMC_XBAR_TWOCHAN 0xc8c 448#define mmMC_XBAR_ARB 0xc8d 449#define mmMC_XBAR_ARB_MAX_BURST 0xc8e 450#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f 451#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90 452#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91 453#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92 454#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93 455#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94 456#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95 457#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96 458#define mmMC_XBAR_SPARE0 0xc97 459#define mmMC_XBAR_SPARE1 0xc98 460#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 461#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 462#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 463#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 464#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 465#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 466#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 467#define mmATC_PERFCOUNTER_LO 0x7a7 468#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 469#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 470#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa 471#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab 472#define mmMC_RPB_PERFCOUNTER_HI 0x7ac 473#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad 474#define mmMC_ARB_PERFCOUNTER_HI 0x7ae 475#define mmATC_PERFCOUNTER_HI 0x7af 476#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 477#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 478#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 479#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 480#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 481#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 482#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 483#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 484#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 485#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 486#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba 487#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb 488#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc 489#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd 490#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be 491#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf 492#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 493#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 494#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 495#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 496#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 497#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 498#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 499#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 500#define mmATC_PERFCOUNTER0_CFG 0x7c8 501#define mmATC_PERFCOUNTER1_CFG 0x7c9 502#define mmATC_PERFCOUNTER2_CFG 0x7ca 503#define mmATC_PERFCOUNTER3_CFG 0x7cb 504#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc 505#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd 506#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce 507#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf 508#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 509#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 510#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 511#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 512#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 513#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 514#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 515#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 516#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 517#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 518#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da 519#define mmMC_GRUB_PERFCOUNTER_LO 0x7e4 520#define mmMC_GRUB_PERFCOUNTER_HI 0x7e5 521#define mmMC_GRUB_PERFCOUNTER0_CFG 0x7e6 522#define mmMC_GRUB_PERFCOUNTER1_CFG 0x7e7 523#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0x7e8 524#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 525#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 526#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 527#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 528#define mmATC_VM_APERTURE0_CNTL 0xcc4 529#define mmATC_VM_APERTURE1_CNTL 0xcc5 530#define mmATC_VM_APERTURE0_CNTL2 0xcc6 531#define mmATC_VM_APERTURE1_CNTL2 0xcc7 532#define mmATC_ATS_CNTL 0xcc9 533#define mmATC_ATS_DEBUG 0xcca 534#define mmATC_ATS_FAULT_DEBUG 0xccb 535#define mmATC_ATS_STATUS 0xccc 536#define mmATC_ATS_FAULT_CNTL 0xccd 537#define mmATC_ATS_FAULT_STATUS_INFO 0xcce 538#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf 539#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 540#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 541#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2 542#define mmATC_MISC_CG 0xcd4 543#define mmATC_L2_CNTL 0xcd5 544#define mmATC_L2_CNTL2 0xcd6 545#define mmATC_L2_DEBUG 0xcd7 546#define mmATC_L2_DEBUG2 0xcd8 547#define mmATC_L2_CACHE_DATA0 0xcd9 548#define mmATC_L2_CACHE_DATA1 0xcda 549#define mmATC_L2_CACHE_DATA2 0xcdb 550#define mmATC_L1_CNTL 0xcdc 551#define mmATC_L1_ADDRESS_OFFSET 0xcdd 552#define mmATC_L1RD_DEBUG_TLB 0xcde 553#define mmATC_L1WR_DEBUG_TLB 0xcdf 554#define mmATC_L1RD_STATUS 0xce0 555#define mmATC_L1WR_STATUS 0xce1 556#define mmATC_L1RD_DEBUG2_TLB 0xce2 557#define mmATC_L1WR_DEBUG2_TLB 0xce3 558#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 559#define mmATC_VMID0_PASID_MAPPING 0xce7 560#define mmATC_VMID1_PASID_MAPPING 0xce8 561#define mmATC_VMID2_PASID_MAPPING 0xce9 562#define mmATC_VMID3_PASID_MAPPING 0xcea 563#define mmATC_VMID4_PASID_MAPPING 0xceb 564#define mmATC_VMID5_PASID_MAPPING 0xcec 565#define mmATC_VMID6_PASID_MAPPING 0xced 566#define mmATC_VMID7_PASID_MAPPING 0xcee 567#define mmATC_VMID8_PASID_MAPPING 0xcef 568#define mmATC_VMID9_PASID_MAPPING 0xcf0 569#define mmATC_VMID10_PASID_MAPPING 0xcf1 570#define mmATC_VMID11_PASID_MAPPING 0xcf2 571#define mmATC_VMID12_PASID_MAPPING 0xcf3 572#define mmATC_VMID13_PASID_MAPPING 0xcf4 573#define mmATC_VMID14_PASID_MAPPING 0xcf5 574#define mmATC_VMID15_PASID_MAPPING 0xcf6 575#define mmATC_ATS_VMID_STATUS 0xd07 576#define mmATC_ATS_SMU_STATUS 0xd08 577#define mmATC_L2_CNTL3 0xd09 578#define mmATC_L2_STATUS 0xd0a 579#define mmATC_L2_STATUS2 0xd0b 580#define mmGMCON_RENG_RAM_INDEX 0xd40 581#define mmGMCON_RENG_RAM_DATA 0xd41 582#define mmGMCON_RENG_EXECUTE 0xd42 583#define mmGMCON_MISC 0xd43 584#define mmGMCON_MISC2 0xd44 585#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 586#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 587#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 588#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 589#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 590#define mmGMCON_PERF_MON_CNTL0 0xd4a 591#define mmGMCON_PERF_MON_CNTL1 0xd4b 592#define mmGMCON_PERF_MON_RSLT0 0xd4c 593#define mmGMCON_PERF_MON_RSLT1 0xd4d 594#define mmGMCON_PGFSM_CONFIG 0xd4e 595#define mmGMCON_PGFSM_WRITE 0xd4f 596#define mmGMCON_PGFSM_READ 0xd50 597#define mmGMCON_MISC3 0xd51 598#define mmGMCON_MASK 0xd52 599#define mmGMCON_LPT_TARGET 0xd53 600#define mmGMCON_DEBUG 0xd5f 601#define mmVM_L2_CNTL 0x500 602#define mmVM_L2_CNTL2 0x501 603#define mmVM_L2_CNTL3 0x502 604#define mmVM_L2_STATUS 0x503 605#define mmVM_CONTEXT0_CNTL 0x504 606#define mmVM_CONTEXT1_CNTL 0x505 607#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 608#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 609#define mmVM_CONTEXT0_CNTL2 0x50c 610#define mmVM_CONTEXT1_CNTL2 0x50d 611#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e 612#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f 613#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 614#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 615#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 616#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 617#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 618#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 619#define mmVM_INVALIDATE_REQUEST 0x51e 620#define mmVM_INVALIDATE_RESPONSE 0x51f 621#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c 622#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d 623#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e 624#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f 625#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 626#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 627#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 628#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 629#define mmVM_PRT_CNTL 0x534 630#define mmVM_CONTEXTS_DISABLE 0x535 631#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 632#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 633#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 634#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 635#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e 636#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f 637#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 638#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 639#define mmVM_FAULT_CLIENT_ID 0x54e 640#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f 641#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 642#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 643#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 644#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 645#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 646#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 647#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 648#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 649#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 650#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f 651#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 652#define mmVM_DEBUG 0x56f 653#define mmVM_L2_CG 0x570 654#define mmVM_L2_BANK_SELECT_MASKA 0x572 655#define mmVM_L2_BANK_SELECT_MASKB 0x573 656#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 657#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 658#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 659#define mmVM_L2_CNTL4 0x578 660#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579 661#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980 662#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981 663#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982 664#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983 665#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984 666#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985 667#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986 668#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987 669#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988 670#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989 671#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a 672#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b 673#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c 674#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d 675#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e 676#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f 677#define mmMC_VM_NB_MMIOBASE 0xf990 678#define mmMC_VM_NB_MMIOLIMIT 0xf991 679#define mmMC_VM_NB_PCI_CTRL 0xf992 680#define mmMC_VM_NB_PCI_ARB 0xf993 681#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994 682#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995 683#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996 684#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997 685#define mmMC_VM_MARC_BASE_LO_0 0xf998 686#define mmMC_VM_MARC_BASE_LO_1 0xf99e 687#define mmMC_VM_MARC_BASE_LO_2 0xf9a4 688#define mmMC_VM_MARC_BASE_LO_3 0xf9aa 689#define mmMC_VM_MARC_BASE_HI_0 0xf999 690#define mmMC_VM_MARC_BASE_HI_1 0xf99f 691#define mmMC_VM_MARC_BASE_HI_2 0xf9a5 692#define mmMC_VM_MARC_BASE_HI_3 0xf9ab 693#define mmMC_VM_MARC_RELOC_LO_0 0xf99a 694#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0 695#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6 696#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac 697#define mmMC_VM_MARC_RELOC_HI_0 0xf99b 698#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1 699#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7 700#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad 701#define mmMC_VM_MARC_LEN_LO_0 0xf99c 702#define mmMC_VM_MARC_LEN_LO_1 0xf9a2 703#define mmMC_VM_MARC_LEN_LO_2 0xf9a8 704#define mmMC_VM_MARC_LEN_LO_3 0xf9ae 705#define mmMC_VM_MARC_LEN_HI_0 0xf99d 706#define mmMC_VM_MARC_LEN_HI_1 0xf9a3 707#define mmMC_VM_MARC_LEN_HI_2 0xf9a9 708#define mmMC_VM_MARC_LEN_HI_3 0xf9af 709#define mmMC_VM_MARC_CNTL 0xf9b0 710#define mmMC_ARB_HARSH_EN_RD 0xdc0 711#define mmMC_ARB_HARSH_EN_WR 0xdc1 712#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 713#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 714#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 715#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 716#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 717#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 718#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 719#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 720#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca 721#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb 722#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc 723#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd 724#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce 725#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf 726#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 727#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 728#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 729#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 730#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 731#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 732#define mmMC_ARB_HARSH_CTL_RD 0xdd6 733#define mmMC_ARB_HARSH_CTL_WR 0xdd7 734#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8 735#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9 736#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda 737#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb 738#define mmMC_FUS_DRAM0_CS0_BASE 0xa05 739#define mmMC_FUS_DRAM1_CS0_BASE 0xa06 740#define mmMC_FUS_DRAM0_CS1_BASE 0xa07 741#define mmMC_FUS_DRAM1_CS1_BASE 0xa08 742#define mmMC_FUS_DRAM0_CS2_BASE 0xa09 743#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a 744#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b 745#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c 746#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d 747#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e 748#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f 749#define mmMC_FUS_DRAM1_CS23_MASK 0xa10 750#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 751#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 752#define mmMC_FUS_DRAM0_CTL_BASE 0xa13 753#define mmMC_FUS_DRAM1_CTL_BASE 0xa14 754#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 755#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 756#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 757#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 758#define mmMC_FUS_DRAM_MODE 0xa19 759#define mmMC_FUS_DRAM_APER_BASE 0xa1a 760#define mmMC_FUS_DRAM_APER_TOP 0xa1b 761#define mmMC_FUS_DRAM_APER_DEF 0xa1e 762#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f 763#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 764#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 765#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 766#define mmMC_CG_DATAPORT 0xa32 767#define mmMC_GRUB_PROBE_MAP 0xa33 768#define mmMC_GRUB_POST_PROBE_DELAY 0xa34 769#define mmMC_GRUB_PROBE_CREDITS 0xa35 770#define mmMC_GRUB_FEATURES 0xa36 771#define mmMC_GRUB_TX_CREDITS 0xa37 772#define mmMC_GRUB_TCB_INDEX 0xa38 773#define mmMC_GRUB_TCB_DATA_LO 0xa39 774#define mmMC_GRUB_TCB_DATA_HI 0xa3a 775#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78 776#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78 777#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 778#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8 779#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 780#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 781#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9 782#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9 783#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a 784#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a 785#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba 786#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa 787#define mmMCIF_WB_BUF_PITCH 0x5e7b 788#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b 789#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb 790#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb 791#define mmMCIF_WB_BUF_1_STATUS 0x5e7c 792#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c 793#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc 794#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc 795#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d 796#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d 797#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd 798#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd 799#define mmMCIF_WB_BUF_2_STATUS 0x5e7e 800#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e 801#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe 802#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe 803#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f 804#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f 805#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf 806#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff 807#define mmMCIF_WB_BUF_3_STATUS 0x5e80 808#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80 809#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0 810#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00 811#define mmMCIF_WB_BUF_3_STATUS2 0x5e81 812#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81 813#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1 814#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01 815#define mmMCIF_WB_BUF_4_STATUS 0x5e82 816#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82 817#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2 818#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02 819#define mmMCIF_WB_BUF_4_STATUS2 0x5e83 820#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83 821#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3 822#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03 823#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84 824#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84 825#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4 826#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04 827#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85 828#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85 829#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5 830#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05 831#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86 832#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86 833#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6 834#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06 835#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87 836#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87 837#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7 838#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07 839#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88 840#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88 841#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8 842#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08 843#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 844#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 845#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9 846#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09 847#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a 848#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a 849#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca 850#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a 851#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b 852#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b 853#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb 854#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b 855#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c 856#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c 857#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc 858#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c 859#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d 860#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d 861#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd 862#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d 863#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e 864#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e 865#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece 866#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e 867#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f 868#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f 869#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf 870#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f 871#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90 872#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90 873#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0 874#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10 875#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 876#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 877#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1 878#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11 879#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92 880#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92 881#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2 882#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12 883#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 884#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 885#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3 886#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13 887#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94 888#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94 889#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4 890#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14 891#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 892#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 893#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5 894#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15 895#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96 896#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96 897#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6 898#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16 899#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 900#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 901#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7 902#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17 903#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 904#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 905#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8 906#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18 907#define mmMCIF_WB_HVVMID_CONTROL 0x5e99 908#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99 909#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9 910#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19 911 912#endif /* GMC_8_2_D_H */ 913