1/* $NetBSD: gc_9_2_1_offset.h,v 1.2 2021/12/18 23:45:14 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _gc_9_2_1_OFFSET_HEADER 24#define _gc_9_2_1_OFFSET_HEADER 25 26 27 28// addressBlock: gc_grbmdec 29// base address: 0x8000 30#define mmGRBM_CNTL 0x0000 31#define mmGRBM_CNTL_BASE_IDX 0 32#define mmGRBM_SKEW_CNTL 0x0001 33#define mmGRBM_SKEW_CNTL_BASE_IDX 0 34#define mmGRBM_STATUS2 0x0002 35#define mmGRBM_STATUS2_BASE_IDX 0 36#define mmGRBM_PWR_CNTL 0x0003 37#define mmGRBM_PWR_CNTL_BASE_IDX 0 38#define mmGRBM_STATUS 0x0004 39#define mmGRBM_STATUS_BASE_IDX 0 40#define mmGRBM_STATUS_SE0 0x0005 41#define mmGRBM_STATUS_SE0_BASE_IDX 0 42#define mmGRBM_STATUS_SE1 0x0006 43#define mmGRBM_STATUS_SE1_BASE_IDX 0 44#define mmGRBM_SOFT_RESET 0x0008 45#define mmGRBM_SOFT_RESET_BASE_IDX 0 46#define mmGRBM_GFX_CLKEN_CNTL 0x000c 47#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 48#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d 49#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 50#define mmGRBM_STATUS_SE2 0x000e 51#define mmGRBM_STATUS_SE2_BASE_IDX 0 52#define mmGRBM_STATUS_SE3 0x000f 53#define mmGRBM_STATUS_SE3_BASE_IDX 0 54#define mmGRBM_READ_ERROR 0x0016 55#define mmGRBM_READ_ERROR_BASE_IDX 0 56#define mmGRBM_READ_ERROR2 0x0017 57#define mmGRBM_READ_ERROR2_BASE_IDX 0 58#define mmGRBM_INT_CNTL 0x0018 59#define mmGRBM_INT_CNTL_BASE_IDX 0 60#define mmGRBM_TRAP_OP 0x0019 61#define mmGRBM_TRAP_OP_BASE_IDX 0 62#define mmGRBM_TRAP_ADDR 0x001a 63#define mmGRBM_TRAP_ADDR_BASE_IDX 0 64#define mmGRBM_TRAP_ADDR_MSK 0x001b 65#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 66#define mmGRBM_TRAP_WD 0x001c 67#define mmGRBM_TRAP_WD_BASE_IDX 0 68#define mmGRBM_TRAP_WD_MSK 0x001d 69#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 70#define mmGRBM_DSM_BYPASS 0x001e 71#define mmGRBM_DSM_BYPASS_BASE_IDX 0 72#define mmGRBM_WRITE_ERROR 0x001f 73#define mmGRBM_WRITE_ERROR_BASE_IDX 0 74#define mmGRBM_IOV_ERROR 0x0020 75#define mmGRBM_IOV_ERROR_BASE_IDX 0 76#define mmGRBM_CHIP_REVISION 0x0021 77#define mmGRBM_CHIP_REVISION_BASE_IDX 0 78#define mmGRBM_GFX_CNTL 0x0022 79#define mmGRBM_GFX_CNTL_BASE_IDX 0 80#define mmGRBM_RSMU_CFG 0x0023 81#define mmGRBM_RSMU_CFG_BASE_IDX 0 82#define mmGRBM_IH_CREDIT 0x0024 83#define mmGRBM_IH_CREDIT_BASE_IDX 0 84#define mmGRBM_PWR_CNTL2 0x0025 85#define mmGRBM_PWR_CNTL2_BASE_IDX 0 86#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 87#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 88#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 89#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 90#define mmGRBM_RSMU_READ_ERROR 0x0028 91#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 92#define mmGRBM_CHICKEN_BITS 0x0029 93#define mmGRBM_CHICKEN_BITS_BASE_IDX 0 94#define mmGRBM_FENCE_RANGE0 0x002a 95#define mmGRBM_FENCE_RANGE0_BASE_IDX 0 96#define mmGRBM_FENCE_RANGE1 0x002b 97#define mmGRBM_FENCE_RANGE1_BASE_IDX 0 98#define mmGRBM_NOWHERE 0x003f 99#define mmGRBM_NOWHERE_BASE_IDX 0 100#define mmGRBM_SCRATCH_REG0 0x0040 101#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 102#define mmGRBM_SCRATCH_REG1 0x0041 103#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 104#define mmGRBM_SCRATCH_REG2 0x0042 105#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 106#define mmGRBM_SCRATCH_REG3 0x0043 107#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 108#define mmGRBM_SCRATCH_REG4 0x0044 109#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 110#define mmGRBM_SCRATCH_REG5 0x0045 111#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 112#define mmGRBM_SCRATCH_REG6 0x0046 113#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 114#define mmGRBM_SCRATCH_REG7 0x0047 115#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 116 117 118// addressBlock: gc_cpdec 119// base address: 0x8200 120#define mmCP_CPC_STATUS 0x0084 121#define mmCP_CPC_STATUS_BASE_IDX 0 122#define mmCP_CPC_BUSY_STAT 0x0085 123#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 124#define mmCP_CPC_STALLED_STAT1 0x0086 125#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 126#define mmCP_CPF_STATUS 0x0087 127#define mmCP_CPF_STATUS_BASE_IDX 0 128#define mmCP_CPF_BUSY_STAT 0x0088 129#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 130#define mmCP_CPF_STALLED_STAT1 0x0089 131#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 132#define mmCP_CPC_GRBM_FREE_COUNT 0x008b 133#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 134#define mmCP_MEC_CNTL 0x008d 135#define mmCP_MEC_CNTL_BASE_IDX 0 136#define mmCP_MEC_ME1_HEADER_DUMP 0x008e 137#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 138#define mmCP_MEC_ME2_HEADER_DUMP 0x008f 139#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 140#define mmCP_CPC_SCRATCH_INDEX 0x0090 141#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 142#define mmCP_CPC_SCRATCH_DATA 0x0091 143#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 144#define mmCP_CPF_GRBM_FREE_COUNT 0x0092 145#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 146#define mmCP_CPC_HALT_HYST_COUNT 0x00a7 147#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 148#define mmCP_CE_COMPARE_COUNT 0x00c0 149#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 150#define mmCP_CE_DE_COUNT 0x00c1 151#define mmCP_CE_DE_COUNT_BASE_IDX 0 152#define mmCP_DE_CE_COUNT 0x00c2 153#define mmCP_DE_CE_COUNT_BASE_IDX 0 154#define mmCP_DE_LAST_INVAL_COUNT 0x00c3 155#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 156#define mmCP_DE_DE_COUNT 0x00c4 157#define mmCP_DE_DE_COUNT_BASE_IDX 0 158#define mmCP_STALLED_STAT3 0x019c 159#define mmCP_STALLED_STAT3_BASE_IDX 0 160#define mmCP_STALLED_STAT1 0x019d 161#define mmCP_STALLED_STAT1_BASE_IDX 0 162#define mmCP_STALLED_STAT2 0x019e 163#define mmCP_STALLED_STAT2_BASE_IDX 0 164#define mmCP_BUSY_STAT 0x019f 165#define mmCP_BUSY_STAT_BASE_IDX 0 166#define mmCP_STAT 0x01a0 167#define mmCP_STAT_BASE_IDX 0 168#define mmCP_ME_HEADER_DUMP 0x01a1 169#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 170#define mmCP_PFP_HEADER_DUMP 0x01a2 171#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 172#define mmCP_GRBM_FREE_COUNT 0x01a3 173#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 174#define mmCP_CE_HEADER_DUMP 0x01a4 175#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 176#define mmCP_PFP_INSTR_PNTR 0x01a5 177#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 178#define mmCP_ME_INSTR_PNTR 0x01a6 179#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 180#define mmCP_CE_INSTR_PNTR 0x01a7 181#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 182#define mmCP_MEC1_INSTR_PNTR 0x01a8 183#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 184#define mmCP_MEC2_INSTR_PNTR 0x01a9 185#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 186#define mmCP_CSF_STAT 0x01b4 187#define mmCP_CSF_STAT_BASE_IDX 0 188#define mmCP_ME_CNTL 0x01b6 189#define mmCP_ME_CNTL_BASE_IDX 0 190#define mmCP_CNTX_STAT 0x01b8 191#define mmCP_CNTX_STAT_BASE_IDX 0 192#define mmCP_ME_PREEMPTION 0x01b9 193#define mmCP_ME_PREEMPTION_BASE_IDX 0 194#define mmCP_ROQ_THRESHOLDS 0x01bc 195#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 196#define mmCP_MEQ_STQ_THRESHOLD 0x01bd 197#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 198#define mmCP_RB2_RPTR 0x01be 199#define mmCP_RB2_RPTR_BASE_IDX 0 200#define mmCP_RB1_RPTR 0x01bf 201#define mmCP_RB1_RPTR_BASE_IDX 0 202#define mmCP_RB0_RPTR 0x01c0 203#define mmCP_RB0_RPTR_BASE_IDX 0 204#define mmCP_RB_RPTR 0x01c0 205#define mmCP_RB_RPTR_BASE_IDX 0 206#define mmCP_RB_WPTR_DELAY 0x01c1 207#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 208#define mmCP_RB_WPTR_POLL_CNTL 0x01c2 209#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 210#define mmCP_ROQ1_THRESHOLDS 0x01d5 211#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 212#define mmCP_ROQ2_THRESHOLDS 0x01d6 213#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 214#define mmCP_STQ_THRESHOLDS 0x01d7 215#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 216#define mmCP_QUEUE_THRESHOLDS 0x01d8 217#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 218#define mmCP_MEQ_THRESHOLDS 0x01d9 219#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 220#define mmCP_ROQ_AVAIL 0x01da 221#define mmCP_ROQ_AVAIL_BASE_IDX 0 222#define mmCP_STQ_AVAIL 0x01db 223#define mmCP_STQ_AVAIL_BASE_IDX 0 224#define mmCP_ROQ2_AVAIL 0x01dc 225#define mmCP_ROQ2_AVAIL_BASE_IDX 0 226#define mmCP_MEQ_AVAIL 0x01dd 227#define mmCP_MEQ_AVAIL_BASE_IDX 0 228#define mmCP_CMD_INDEX 0x01de 229#define mmCP_CMD_INDEX_BASE_IDX 0 230#define mmCP_CMD_DATA 0x01df 231#define mmCP_CMD_DATA_BASE_IDX 0 232#define mmCP_ROQ_RB_STAT 0x01e0 233#define mmCP_ROQ_RB_STAT_BASE_IDX 0 234#define mmCP_ROQ_IB1_STAT 0x01e1 235#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 236#define mmCP_ROQ_IB2_STAT 0x01e2 237#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 238#define mmCP_STQ_STAT 0x01e3 239#define mmCP_STQ_STAT_BASE_IDX 0 240#define mmCP_STQ_WR_STAT 0x01e4 241#define mmCP_STQ_WR_STAT_BASE_IDX 0 242#define mmCP_MEQ_STAT 0x01e5 243#define mmCP_MEQ_STAT_BASE_IDX 0 244#define mmCP_CEQ1_AVAIL 0x01e6 245#define mmCP_CEQ1_AVAIL_BASE_IDX 0 246#define mmCP_CEQ2_AVAIL 0x01e7 247#define mmCP_CEQ2_AVAIL_BASE_IDX 0 248#define mmCP_CE_ROQ_RB_STAT 0x01e8 249#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 250#define mmCP_CE_ROQ_IB1_STAT 0x01e9 251#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 252#define mmCP_CE_ROQ_IB2_STAT 0x01ea 253#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 254 255 256// addressBlock: gc_padec 257// base address: 0x8800 258#define mmVGT_VTX_VECT_EJECT_REG 0x022c 259#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 260#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d 261#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 262#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e 263#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 264#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f 265#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 266#define mmVGT_LAST_COPY_STATE 0x0230 267#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 268#define mmVGT_CACHE_INVALIDATION 0x0231 269#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 270#define mmVGT_STRMOUT_DELAY 0x0233 271#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 272#define mmVGT_FIFO_DEPTHS 0x0234 273#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 274#define mmVGT_GS_VERTEX_REUSE 0x0235 275#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 276#define mmVGT_MC_LAT_CNTL 0x0236 277#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 278#define mmIA_CNTL_STATUS 0x0237 279#define mmIA_CNTL_STATUS_BASE_IDX 0 280#define mmVGT_CNTL_STATUS 0x023c 281#define mmVGT_CNTL_STATUS_BASE_IDX 0 282#define mmWD_CNTL_STATUS 0x023f 283#define mmWD_CNTL_STATUS_BASE_IDX 0 284#define mmCC_GC_PRIM_CONFIG 0x0240 285#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 286#define mmGC_USER_PRIM_CONFIG 0x0241 287#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 288#define mmWD_QOS 0x0242 289#define mmWD_QOS_BASE_IDX 0 290#define mmWD_UTCL1_CNTL 0x0243 291#define mmWD_UTCL1_CNTL_BASE_IDX 0 292#define mmWD_UTCL1_STATUS 0x0244 293#define mmWD_UTCL1_STATUS_BASE_IDX 0 294#define mmIA_UTCL1_CNTL 0x0246 295#define mmIA_UTCL1_CNTL_BASE_IDX 0 296#define mmIA_UTCL1_STATUS 0x0247 297#define mmIA_UTCL1_STATUS_BASE_IDX 0 298#define mmVGT_SYS_CONFIG 0x0263 299#define mmVGT_SYS_CONFIG_BASE_IDX 0 300#define mmVGT_VS_MAX_WAVE_ID 0x0268 301#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 302#define mmVGT_GS_MAX_WAVE_ID 0x0269 303#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 304#define mmGFX_PIPE_CONTROL 0x026d 305#define mmGFX_PIPE_CONTROL_BASE_IDX 0 306#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f 307#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 308#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270 309#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 310#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271 311#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 312#define mmVGT_DMA_CONTROL 0x0272 313#define mmVGT_DMA_CONTROL_BASE_IDX 0 314#define mmVGT_DMA_LS_HS_CONFIG 0x0273 315#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 316#define mmWD_BUF_RESOURCE_1 0x0276 317#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 318#define mmWD_BUF_RESOURCE_2 0x0277 319#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 320#define mmPA_CL_CNTL_STATUS 0x0284 321#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 322#define mmPA_CL_ENHANCE 0x0285 323#define mmPA_CL_ENHANCE_BASE_IDX 0 324#define mmPA_SU_CNTL_STATUS 0x0294 325#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 326#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295 327#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 328#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 329#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 330#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 331#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 332#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 333#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 334#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 335#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 336#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc 337#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 338#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd 339#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 340#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce 341#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 342#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf 343#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 344#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 345#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 346#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1 347#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 348#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2 349#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 350#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3 351#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 352#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4 353#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 354#define mmPA_SC_ENHANCE_2 0x02dc 355#define mmPA_SC_ENHANCE_2_BASE_IDX 0 356#define mmPA_SC_FIFO_SIZE 0x02f3 357#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 358#define mmPA_SC_IF_FIFO_SIZE 0x02f5 359#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 360#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 361#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 362#define mmPA_UTCL1_CNTL1 0x02f9 363#define mmPA_UTCL1_CNTL1_BASE_IDX 0 364#define mmPA_UTCL1_CNTL2 0x02fa 365#define mmPA_UTCL1_CNTL2_BASE_IDX 0 366#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb 367#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 368#define mmPA_SC_ENHANCE 0x02fc 369#define mmPA_SC_ENHANCE_BASE_IDX 0 370#define mmPA_SC_ENHANCE_1 0x02fd 371#define mmPA_SC_ENHANCE_1_BASE_IDX 0 372#define mmPA_SC_DSM_CNTL 0x02fe 373#define mmPA_SC_DSM_CNTL_BASE_IDX 0 374#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff 375#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 376 377 378// addressBlock: gc_sqdec 379// base address: 0x8c00 380#define mmSQ_CONFIG 0x0300 381#define mmSQ_CONFIG_BASE_IDX 0 382#define mmSQC_CONFIG 0x0301 383#define mmSQC_CONFIG_BASE_IDX 0 384#define mmLDS_CONFIG 0x0302 385#define mmLDS_CONFIG_BASE_IDX 0 386#define mmSQ_RANDOM_WAVE_PRI 0x0303 387#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 388#define mmSQ_REG_CREDITS 0x0304 389#define mmSQ_REG_CREDITS_BASE_IDX 0 390#define mmSQ_FIFO_SIZES 0x0305 391#define mmSQ_FIFO_SIZES_BASE_IDX 0 392#define mmSQ_DSM_CNTL 0x0306 393#define mmSQ_DSM_CNTL_BASE_IDX 0 394#define mmSQ_DSM_CNTL2 0x0307 395#define mmSQ_DSM_CNTL2_BASE_IDX 0 396#define mmSQ_RUNTIME_CONFIG 0x0308 397#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 398#define mmSH_MEM_BASES 0x030a 399#define mmSH_MEM_BASES_BASE_IDX 0 400#define mmSH_MEM_CONFIG 0x030d 401#define mmSH_MEM_CONFIG_BASE_IDX 0 402#define mmCC_GC_SHADER_RATE_CONFIG 0x0312 403#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 404#define mmGC_USER_SHADER_RATE_CONFIG 0x0313 405#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 406#define mmSQ_INTERRUPT_AUTO_MASK 0x0314 407#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 408#define mmSQ_INTERRUPT_MSG_CTRL 0x0315 409#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 410#define mmSQ_UTCL1_CNTL1 0x0317 411#define mmSQ_UTCL1_CNTL1_BASE_IDX 0 412#define mmSQ_UTCL1_CNTL2 0x0318 413#define mmSQ_UTCL1_CNTL2_BASE_IDX 0 414#define mmSQ_UTCL1_STATUS 0x0319 415#define mmSQ_UTCL1_STATUS_BASE_IDX 0 416#define mmSQ_SHADER_TBA_LO 0x031c 417#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 418#define mmSQ_SHADER_TBA_HI 0x031d 419#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 420#define mmSQ_SHADER_TMA_LO 0x031e 421#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 422#define mmSQ_SHADER_TMA_HI 0x031f 423#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 424#define mmSQC_DSM_CNTL 0x0320 425#define mmSQC_DSM_CNTL_BASE_IDX 0 426#define mmSQC_DSM_CNTLA 0x0321 427#define mmSQC_DSM_CNTLA_BASE_IDX 0 428#define mmSQC_DSM_CNTLB 0x0322 429#define mmSQC_DSM_CNTLB_BASE_IDX 0 430#define mmSQC_DSM_CNTL2 0x0325 431#define mmSQC_DSM_CNTL2_BASE_IDX 0 432#define mmSQC_DSM_CNTL2A 0x0326 433#define mmSQC_DSM_CNTL2A_BASE_IDX 0 434#define mmSQC_DSM_CNTL2B 0x0327 435#define mmSQC_DSM_CNTL2B_BASE_IDX 0 436#define mmSQ_REG_TIMESTAMP 0x0374 437#define mmSQ_REG_TIMESTAMP_BASE_IDX 0 438#define mmSQ_CMD_TIMESTAMP 0x0375 439#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0 440#define mmSQ_IND_INDEX 0x0378 441#define mmSQ_IND_INDEX_BASE_IDX 0 442#define mmSQ_IND_DATA 0x0379 443#define mmSQ_IND_DATA_BASE_IDX 0 444#define mmSQ_CMD 0x037b 445#define mmSQ_CMD_BASE_IDX 0 446#define mmSQ_TIME_HI 0x037c 447#define mmSQ_TIME_HI_BASE_IDX 0 448#define mmSQ_TIME_LO 0x037d 449#define mmSQ_TIME_LO_BASE_IDX 0 450#define mmSQ_DS_0 0x037f 451#define mmSQ_DS_0_BASE_IDX 0 452#define mmSQ_DS_1 0x037f 453#define mmSQ_DS_1_BASE_IDX 0 454#define mmSQ_EXP_0 0x037f 455#define mmSQ_EXP_0_BASE_IDX 0 456#define mmSQ_EXP_1 0x037f 457#define mmSQ_EXP_1_BASE_IDX 0 458#define mmSQ_FLAT_0 0x037f 459#define mmSQ_FLAT_0_BASE_IDX 0 460#define mmSQ_FLAT_1 0x037f 461#define mmSQ_FLAT_1_BASE_IDX 0 462#define mmSQ_GLBL_0 0x037f 463#define mmSQ_GLBL_0_BASE_IDX 0 464#define mmSQ_GLBL_1 0x037f 465#define mmSQ_GLBL_1_BASE_IDX 0 466#define mmSQ_INST 0x037f 467#define mmSQ_INST_BASE_IDX 0 468#define mmSQ_MIMG_0 0x037f 469#define mmSQ_MIMG_0_BASE_IDX 0 470#define mmSQ_MIMG_1 0x037f 471#define mmSQ_MIMG_1_BASE_IDX 0 472#define mmSQ_MTBUF_0 0x037f 473#define mmSQ_MTBUF_0_BASE_IDX 0 474#define mmSQ_MTBUF_1 0x037f 475#define mmSQ_MTBUF_1_BASE_IDX 0 476#define mmSQ_MUBUF_0 0x037f 477#define mmSQ_MUBUF_0_BASE_IDX 0 478#define mmSQ_MUBUF_1 0x037f 479#define mmSQ_MUBUF_1_BASE_IDX 0 480#define mmSQ_SCRATCH_0 0x037f 481#define mmSQ_SCRATCH_0_BASE_IDX 0 482#define mmSQ_SCRATCH_1 0x037f 483#define mmSQ_SCRATCH_1_BASE_IDX 0 484#define mmSQ_SMEM_0 0x037f 485#define mmSQ_SMEM_0_BASE_IDX 0 486#define mmSQ_SMEM_1 0x037f 487#define mmSQ_SMEM_1_BASE_IDX 0 488#define mmSQ_SOP1 0x037f 489#define mmSQ_SOP1_BASE_IDX 0 490#define mmSQ_SOP2 0x037f 491#define mmSQ_SOP2_BASE_IDX 0 492#define mmSQ_SOPC 0x037f 493#define mmSQ_SOPC_BASE_IDX 0 494#define mmSQ_SOPK 0x037f 495#define mmSQ_SOPK_BASE_IDX 0 496#define mmSQ_SOPP 0x037f 497#define mmSQ_SOPP_BASE_IDX 0 498#define mmSQ_VINTRP 0x037f 499#define mmSQ_VINTRP_BASE_IDX 0 500#define mmSQ_VOP1 0x037f 501#define mmSQ_VOP1_BASE_IDX 0 502#define mmSQ_VOP2 0x037f 503#define mmSQ_VOP2_BASE_IDX 0 504#define mmSQ_VOP3P_0 0x037f 505#define mmSQ_VOP3P_0_BASE_IDX 0 506#define mmSQ_VOP3P_1 0x037f 507#define mmSQ_VOP3P_1_BASE_IDX 0 508#define mmSQ_VOP3_0 0x037f 509#define mmSQ_VOP3_0_BASE_IDX 0 510#define mmSQ_VOP3_0_SDST_ENC 0x037f 511#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0 512#define mmSQ_VOP3_1 0x037f 513#define mmSQ_VOP3_1_BASE_IDX 0 514#define mmSQ_VOPC 0x037f 515#define mmSQ_VOPC_BASE_IDX 0 516#define mmSQ_VOP_DPP 0x037f 517#define mmSQ_VOP_DPP_BASE_IDX 0 518#define mmSQ_VOP_SDWA 0x037f 519#define mmSQ_VOP_SDWA_BASE_IDX 0 520#define mmSQ_VOP_SDWA_SDST_ENC 0x037f 521#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 522#define mmSQ_LB_CTR_CTRL 0x0398 523#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 524#define mmSQ_LB_DATA0 0x0399 525#define mmSQ_LB_DATA0_BASE_IDX 0 526#define mmSQ_LB_DATA1 0x039a 527#define mmSQ_LB_DATA1_BASE_IDX 0 528#define mmSQ_LB_DATA2 0x039b 529#define mmSQ_LB_DATA2_BASE_IDX 0 530#define mmSQ_LB_DATA3 0x039c 531#define mmSQ_LB_DATA3_BASE_IDX 0 532#define mmSQ_LB_CTR_SEL 0x039d 533#define mmSQ_LB_CTR_SEL_BASE_IDX 0 534#define mmSQ_LB_CTR0_CU 0x039e 535#define mmSQ_LB_CTR0_CU_BASE_IDX 0 536#define mmSQ_LB_CTR1_CU 0x039f 537#define mmSQ_LB_CTR1_CU_BASE_IDX 0 538#define mmSQ_LB_CTR2_CU 0x03a0 539#define mmSQ_LB_CTR2_CU_BASE_IDX 0 540#define mmSQ_LB_CTR3_CU 0x03a1 541#define mmSQ_LB_CTR3_CU_BASE_IDX 0 542#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0 543#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 544#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0 545#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 546#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0 547#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 548#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 549#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 550#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 551#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 552#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 553#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 554#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0 555#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 556#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 557#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 558#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 559#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 560#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 561#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 562#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 563#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 564#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 565#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 566#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 567#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 568#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0 569#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 570#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 571#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 572#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 573#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 574#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 575#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 576#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 577#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 578#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 579#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 580#define mmSQ_WREXEC_EXEC_HI 0x03b1 581#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 582#define mmSQ_WREXEC_EXEC_LO 0x03b1 583#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 584#define mmSQ_BUF_RSRC_WORD0 0x03c0 585#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0 586#define mmSQ_BUF_RSRC_WORD1 0x03c1 587#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0 588#define mmSQ_BUF_RSRC_WORD2 0x03c2 589#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0 590#define mmSQ_BUF_RSRC_WORD3 0x03c3 591#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0 592#define mmSQ_IMG_RSRC_WORD0 0x03c4 593#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0 594#define mmSQ_IMG_RSRC_WORD1 0x03c5 595#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0 596#define mmSQ_IMG_RSRC_WORD2 0x03c6 597#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0 598#define mmSQ_IMG_RSRC_WORD3 0x03c7 599#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0 600#define mmSQ_IMG_RSRC_WORD4 0x03c8 601#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0 602#define mmSQ_IMG_RSRC_WORD5 0x03c9 603#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0 604#define mmSQ_IMG_RSRC_WORD6 0x03ca 605#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0 606#define mmSQ_IMG_RSRC_WORD7 0x03cb 607#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0 608#define mmSQ_IMG_SAMP_WORD0 0x03cc 609#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0 610#define mmSQ_IMG_SAMP_WORD1 0x03cd 611#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0 612#define mmSQ_IMG_SAMP_WORD2 0x03ce 613#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0 614#define mmSQ_IMG_SAMP_WORD3 0x03cf 615#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0 616#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0 617#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 618#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1 619#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 620#define mmSQ_M0_GPR_IDX_WORD 0x03d2 621#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0 622#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3 623#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 624#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4 625#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 626#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5 627#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 628#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6 629#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 630#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7 631#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 632#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8 633#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 634 635 636// addressBlock: gc_shsdec 637// base address: 0x9000 638#define mmSX_DEBUG_1 0x0419 639#define mmSX_DEBUG_1_BASE_IDX 0 640#define mmSPI_PS_MAX_WAVE_ID 0x043a 641#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 642#define mmSPI_START_PHASE 0x043b 643#define mmSPI_START_PHASE_BASE_IDX 0 644#define mmSPI_GFX_CNTL 0x043c 645#define mmSPI_GFX_CNTL_BASE_IDX 0 646#define mmSPI_DSM_CNTL 0x0443 647#define mmSPI_DSM_CNTL_BASE_IDX 0 648#define mmSPI_DSM_CNTL2 0x0444 649#define mmSPI_DSM_CNTL2_BASE_IDX 0 650#define mmSPI_CONFIG_PS_CU_EN 0x0452 651#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 652#define mmSPI_WF_LIFETIME_CNTL 0x04aa 653#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 654#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab 655#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 656#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac 657#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 658#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad 659#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 660#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae 661#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 662#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af 663#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 664#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0 665#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 666#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1 667#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 668#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2 669#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 670#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3 671#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 672#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4 673#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 674#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5 675#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 676#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6 677#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 678#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7 679#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 680#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8 681#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 682#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9 683#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 684#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba 685#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 686#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb 687#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 688#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc 689#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 690#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd 691#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 692#define mmSPI_WF_LIFETIME_STATUS_9 0x04be 693#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 694#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf 695#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 696#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0 697#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 698#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1 699#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 700#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2 701#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 702#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3 703#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 704#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4 705#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 706#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5 707#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 708#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6 709#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 710#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7 711#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 712#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8 713#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 714#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9 715#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 716#define mmSPI_LB_CTR_CTRL 0x04d4 717#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 718#define mmSPI_LB_CU_MASK 0x04d5 719#define mmSPI_LB_CU_MASK_BASE_IDX 0 720#define mmSPI_LB_DATA_REG 0x04d6 721#define mmSPI_LB_DATA_REG_BASE_IDX 0 722#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 723#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 724#define mmSPI_GDS_CREDITS 0x04d8 725#define mmSPI_GDS_CREDITS_BASE_IDX 0 726#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 727#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 728#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da 729#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 730#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db 731#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 732#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc 733#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 734#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd 735#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 736#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de 737#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 738#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df 739#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 740#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 741#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 742#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 743#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 744#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 745#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 746#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 747#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 748#define mmSPI_LB_DATA_WAVES 0x04e4 749#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 750#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 751#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 752#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 753#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 754#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 755#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 756#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec 757#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 758#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed 759#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 760#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee 761#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 762#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef 763#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 764#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 765#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 766#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 767#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 768#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 769#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 770#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 771#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 772#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 773#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 774#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 775#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 776 777 778// addressBlock: gc_tpdec 779// base address: 0x9400 780#define mmTD_CNTL 0x0525 781#define mmTD_CNTL_BASE_IDX 0 782#define mmTD_STATUS 0x0526 783#define mmTD_STATUS_BASE_IDX 0 784#define mmTD_DSM_CNTL 0x052f 785#define mmTD_DSM_CNTL_BASE_IDX 0 786#define mmTD_DSM_CNTL2 0x0530 787#define mmTD_DSM_CNTL2_BASE_IDX 0 788#define mmTD_SCRATCH 0x0533 789#define mmTD_SCRATCH_BASE_IDX 0 790#define mmTA_CNTL 0x0541 791#define mmTA_CNTL_BASE_IDX 0 792#define mmTA_CNTL_AUX 0x0542 793#define mmTA_CNTL_AUX_BASE_IDX 0 794#define mmTA_RESERVED_010C 0x0543 795#define mmTA_RESERVED_010C_BASE_IDX 0 796#define mmTA_STATUS 0x0548 797#define mmTA_STATUS_BASE_IDX 0 798#define mmTA_SCRATCH 0x0564 799#define mmTA_SCRATCH_BASE_IDX 0 800 801 802// addressBlock: gc_gdsdec 803// base address: 0x9700 804#define mmGDS_CONFIG 0x05c0 805#define mmGDS_CONFIG_BASE_IDX 0 806#define mmGDS_CNTL_STATUS 0x05c1 807#define mmGDS_CNTL_STATUS_BASE_IDX 0 808#define mmGDS_ENHANCE2 0x05c2 809#define mmGDS_ENHANCE2_BASE_IDX 0 810#define mmGDS_PROTECTION_FAULT 0x05c3 811#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 812#define mmGDS_VM_PROTECTION_FAULT 0x05c4 813#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 814#define mmGDS_DSM_CNTL 0x05ca 815#define mmGDS_DSM_CNTL_BASE_IDX 0 816#define mmGDS_DSM_CNTL2 0x05cd 817#define mmGDS_DSM_CNTL2_BASE_IDX 0 818#define mmGDS_WD_GDS_CSB 0x05ce 819#define mmGDS_WD_GDS_CSB_BASE_IDX 0 820 821 822// addressBlock: gc_rbdec 823// base address: 0x9800 824#define mmDB_DEBUG 0x060c 825#define mmDB_DEBUG_BASE_IDX 0 826#define mmDB_DEBUG2 0x060d 827#define mmDB_DEBUG2_BASE_IDX 0 828#define mmDB_DEBUG3 0x060e 829#define mmDB_DEBUG3_BASE_IDX 0 830#define mmDB_DEBUG4 0x060f 831#define mmDB_DEBUG4_BASE_IDX 0 832#define mmDB_CREDIT_LIMIT 0x0614 833#define mmDB_CREDIT_LIMIT_BASE_IDX 0 834#define mmDB_WATERMARKS 0x0615 835#define mmDB_WATERMARKS_BASE_IDX 0 836#define mmDB_SUBTILE_CONTROL 0x0616 837#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 838#define mmDB_FREE_CACHELINES 0x0617 839#define mmDB_FREE_CACHELINES_BASE_IDX 0 840#define mmDB_FIFO_DEPTH1 0x0618 841#define mmDB_FIFO_DEPTH1_BASE_IDX 0 842#define mmDB_FIFO_DEPTH2 0x0619 843#define mmDB_FIFO_DEPTH2_BASE_IDX 0 844#define mmDB_EXCEPTION_CONTROL 0x061a 845#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 846#define mmDB_RING_CONTROL 0x061b 847#define mmDB_RING_CONTROL_BASE_IDX 0 848#define mmDB_MEM_ARB_WATERMARKS 0x061c 849#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 850#define mmDB_RMI_CACHE_POLICY 0x061e 851#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0 852#define mmDB_DFSM_CONFIG 0x0630 853#define mmDB_DFSM_CONFIG_BASE_IDX 0 854#define mmDB_DFSM_WATERMARK 0x0631 855#define mmDB_DFSM_WATERMARK_BASE_IDX 0 856#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632 857#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 858#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633 859#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 860#define mmDB_DFSM_WATCHDOG 0x0634 861#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 862#define mmDB_DFSM_FLUSH_ENABLE 0x0635 863#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 864#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636 865#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 866#define mmCC_RB_REDUNDANCY 0x063c 867#define mmCC_RB_REDUNDANCY_BASE_IDX 0 868#define mmCC_RB_BACKEND_DISABLE 0x063d 869#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 870#define mmGB_ADDR_CONFIG 0x063e 871#define mmGB_ADDR_CONFIG_BASE_IDX 0 872#define mmGB_BACKEND_MAP 0x063f 873#define mmGB_BACKEND_MAP_BASE_IDX 0 874#define mmGB_GPU_ID 0x0640 875#define mmGB_GPU_ID_BASE_IDX 0 876#define mmCC_RB_DAISY_CHAIN 0x0641 877#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 878#define mmGB_ADDR_CONFIG_READ 0x0642 879#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 880#define mmGB_TILE_MODE0 0x0644 881#define mmGB_TILE_MODE0_BASE_IDX 0 882#define mmGB_TILE_MODE1 0x0645 883#define mmGB_TILE_MODE1_BASE_IDX 0 884#define mmGB_TILE_MODE2 0x0646 885#define mmGB_TILE_MODE2_BASE_IDX 0 886#define mmGB_TILE_MODE3 0x0647 887#define mmGB_TILE_MODE3_BASE_IDX 0 888#define mmGB_TILE_MODE4 0x0648 889#define mmGB_TILE_MODE4_BASE_IDX 0 890#define mmGB_TILE_MODE5 0x0649 891#define mmGB_TILE_MODE5_BASE_IDX 0 892#define mmGB_TILE_MODE6 0x064a 893#define mmGB_TILE_MODE6_BASE_IDX 0 894#define mmGB_TILE_MODE7 0x064b 895#define mmGB_TILE_MODE7_BASE_IDX 0 896#define mmGB_TILE_MODE8 0x064c 897#define mmGB_TILE_MODE8_BASE_IDX 0 898#define mmGB_TILE_MODE9 0x064d 899#define mmGB_TILE_MODE9_BASE_IDX 0 900#define mmGB_TILE_MODE10 0x064e 901#define mmGB_TILE_MODE10_BASE_IDX 0 902#define mmGB_TILE_MODE11 0x064f 903#define mmGB_TILE_MODE11_BASE_IDX 0 904#define mmGB_TILE_MODE12 0x0650 905#define mmGB_TILE_MODE12_BASE_IDX 0 906#define mmGB_TILE_MODE13 0x0651 907#define mmGB_TILE_MODE13_BASE_IDX 0 908#define mmGB_TILE_MODE14 0x0652 909#define mmGB_TILE_MODE14_BASE_IDX 0 910#define mmGB_TILE_MODE15 0x0653 911#define mmGB_TILE_MODE15_BASE_IDX 0 912#define mmGB_TILE_MODE16 0x0654 913#define mmGB_TILE_MODE16_BASE_IDX 0 914#define mmGB_TILE_MODE17 0x0655 915#define mmGB_TILE_MODE17_BASE_IDX 0 916#define mmGB_TILE_MODE18 0x0656 917#define mmGB_TILE_MODE18_BASE_IDX 0 918#define mmGB_TILE_MODE19 0x0657 919#define mmGB_TILE_MODE19_BASE_IDX 0 920#define mmGB_TILE_MODE20 0x0658 921#define mmGB_TILE_MODE20_BASE_IDX 0 922#define mmGB_TILE_MODE21 0x0659 923#define mmGB_TILE_MODE21_BASE_IDX 0 924#define mmGB_TILE_MODE22 0x065a 925#define mmGB_TILE_MODE22_BASE_IDX 0 926#define mmGB_TILE_MODE23 0x065b 927#define mmGB_TILE_MODE23_BASE_IDX 0 928#define mmGB_TILE_MODE24 0x065c 929#define mmGB_TILE_MODE24_BASE_IDX 0 930#define mmGB_TILE_MODE25 0x065d 931#define mmGB_TILE_MODE25_BASE_IDX 0 932#define mmGB_TILE_MODE26 0x065e 933#define mmGB_TILE_MODE26_BASE_IDX 0 934#define mmGB_TILE_MODE27 0x065f 935#define mmGB_TILE_MODE27_BASE_IDX 0 936#define mmGB_TILE_MODE28 0x0660 937#define mmGB_TILE_MODE28_BASE_IDX 0 938#define mmGB_TILE_MODE29 0x0661 939#define mmGB_TILE_MODE29_BASE_IDX 0 940#define mmGB_TILE_MODE30 0x0662 941#define mmGB_TILE_MODE30_BASE_IDX 0 942#define mmGB_TILE_MODE31 0x0663 943#define mmGB_TILE_MODE31_BASE_IDX 0 944#define mmGB_MACROTILE_MODE0 0x0664 945#define mmGB_MACROTILE_MODE0_BASE_IDX 0 946#define mmGB_MACROTILE_MODE1 0x0665 947#define mmGB_MACROTILE_MODE1_BASE_IDX 0 948#define mmGB_MACROTILE_MODE2 0x0666 949#define mmGB_MACROTILE_MODE2_BASE_IDX 0 950#define mmGB_MACROTILE_MODE3 0x0667 951#define mmGB_MACROTILE_MODE3_BASE_IDX 0 952#define mmGB_MACROTILE_MODE4 0x0668 953#define mmGB_MACROTILE_MODE4_BASE_IDX 0 954#define mmGB_MACROTILE_MODE5 0x0669 955#define mmGB_MACROTILE_MODE5_BASE_IDX 0 956#define mmGB_MACROTILE_MODE6 0x066a 957#define mmGB_MACROTILE_MODE6_BASE_IDX 0 958#define mmGB_MACROTILE_MODE7 0x066b 959#define mmGB_MACROTILE_MODE7_BASE_IDX 0 960#define mmGB_MACROTILE_MODE8 0x066c 961#define mmGB_MACROTILE_MODE8_BASE_IDX 0 962#define mmGB_MACROTILE_MODE9 0x066d 963#define mmGB_MACROTILE_MODE9_BASE_IDX 0 964#define mmGB_MACROTILE_MODE10 0x066e 965#define mmGB_MACROTILE_MODE10_BASE_IDX 0 966#define mmGB_MACROTILE_MODE11 0x066f 967#define mmGB_MACROTILE_MODE11_BASE_IDX 0 968#define mmGB_MACROTILE_MODE12 0x0670 969#define mmGB_MACROTILE_MODE12_BASE_IDX 0 970#define mmGB_MACROTILE_MODE13 0x0671 971#define mmGB_MACROTILE_MODE13_BASE_IDX 0 972#define mmGB_MACROTILE_MODE14 0x0672 973#define mmGB_MACROTILE_MODE14_BASE_IDX 0 974#define mmGB_MACROTILE_MODE15 0x0673 975#define mmGB_MACROTILE_MODE15_BASE_IDX 0 976#define mmCB_HW_CONTROL 0x0680 977#define mmCB_HW_CONTROL_BASE_IDX 0 978#define mmCB_HW_CONTROL_1 0x0681 979#define mmCB_HW_CONTROL_1_BASE_IDX 0 980#define mmCB_HW_CONTROL_2 0x0682 981#define mmCB_HW_CONTROL_2_BASE_IDX 0 982#define mmCB_HW_CONTROL_3 0x0683 983#define mmCB_HW_CONTROL_3_BASE_IDX 0 984#define mmCB_HW_MEM_ARBITER_RD 0x0686 985#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 986#define mmCB_HW_MEM_ARBITER_WR 0x0687 987#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 988#define mmCB_DCC_CONFIG 0x0688 989#define mmCB_DCC_CONFIG_BASE_IDX 0 990#define mmGC_USER_RB_REDUNDANCY 0x06de 991#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 992#define mmGC_USER_RB_BACKEND_DISABLE 0x06df 993#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 994 995 996// addressBlock: gc_ea_gceadec2 997// base address: 0x9c00 998#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 999#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1000#define mmGCEA_DSM_CNTL 0x0708 1001#define mmGCEA_DSM_CNTL_BASE_IDX 0 1002#define mmGCEA_DSM_CNTLA 0x0709 1003#define mmGCEA_DSM_CNTLA_BASE_IDX 0 1004#define mmGCEA_DSM_CNTLB 0x070a 1005#define mmGCEA_DSM_CNTLB_BASE_IDX 0 1006#define mmGCEA_DSM_CNTL2 0x070b 1007#define mmGCEA_DSM_CNTL2_BASE_IDX 0 1008#define mmGCEA_DSM_CNTL2A 0x070c 1009#define mmGCEA_DSM_CNTL2A_BASE_IDX 0 1010#define mmGCEA_DSM_CNTL2B 0x070d 1011#define mmGCEA_DSM_CNTL2B_BASE_IDX 0 1012#define mmGCEA_TCC_XBR_CREDITS 0x070e 1013#define mmGCEA_TCC_XBR_CREDITS_BASE_IDX 0 1014#define mmGCEA_TCC_XBR_MAXBURST 0x070f 1015#define mmGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 1016#define mmGCEA_PROBE_CNTL 0x0710 1017#define mmGCEA_PROBE_CNTL_BASE_IDX 0 1018#define mmGCEA_PROBE_MAP 0x0711 1019#define mmGCEA_PROBE_MAP_BASE_IDX 0 1020#define mmGCEA_ERR_STATUS 0x0712 1021#define mmGCEA_ERR_STATUS_BASE_IDX 0 1022#define mmGCEA_MISC2 0x0713 1023#define mmGCEA_MISC2_BASE_IDX 0 1024#define mmGCEA_DRAM_BANK_ARB 0x0714 1025#define mmGCEA_DRAM_BANK_ARB_BASE_IDX 0 1026#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x0715 1027#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 1028#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0716 1029#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 1030#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x0717 1031#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 1032#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x0718 1033#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 1034#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 1035#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 1036#define mmGCEA_SDP_ENABLE 0x071a 1037#define mmGCEA_SDP_ENABLE_BASE_IDX 0 1038 1039 1040// addressBlock: gc_rmi_rmidec 1041// base address: 0x9e00 1042#define mmRMI_GENERAL_CNTL 0x0780 1043#define mmRMI_GENERAL_CNTL_BASE_IDX 0 1044#define mmRMI_GENERAL_CNTL1 0x0781 1045#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 1046#define mmRMI_GENERAL_STATUS 0x0782 1047#define mmRMI_GENERAL_STATUS_BASE_IDX 0 1048#define mmRMI_SUBBLOCK_STATUS0 0x0783 1049#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 1050#define mmRMI_SUBBLOCK_STATUS1 0x0784 1051#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 1052#define mmRMI_SUBBLOCK_STATUS2 0x0785 1053#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 1054#define mmRMI_SUBBLOCK_STATUS3 0x0786 1055#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 1056#define mmRMI_XBAR_CONFIG 0x0787 1057#define mmRMI_XBAR_CONFIG_BASE_IDX 0 1058#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788 1059#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 1060#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789 1061#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 1062#define mmRMI_DEMUX_CNTL 0x078a 1063#define mmRMI_DEMUX_CNTL_BASE_IDX 0 1064#define mmRMI_UTCL1_CNTL1 0x078b 1065#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 1066#define mmRMI_UTCL1_CNTL2 0x078c 1067#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 1068#define mmRMI_UTC_UNIT_CONFIG 0x078d 1069#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 1070#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e 1071#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 1072#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f 1073#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 1074#define mmRMI_SCOREBOARD_CNTL 0x0790 1075#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 1076#define mmRMI_SCOREBOARD_STATUS0 0x0791 1077#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 1078#define mmRMI_SCOREBOARD_STATUS1 0x0792 1079#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 1080#define mmRMI_SCOREBOARD_STATUS2 0x0793 1081#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 1082#define mmRMI_XBAR_ARBITER_CONFIG 0x0794 1083#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 1084#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795 1085#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 1086#define mmRMI_CLOCK_CNTRL 0x0796 1087#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 1088#define mmRMI_UTCL1_STATUS 0x0797 1089#define mmRMI_UTCL1_STATUS_BASE_IDX 0 1090#define mmRMI_SPARE 0x079e 1091#define mmRMI_SPARE_BASE_IDX 0 1092#define mmRMI_SPARE_1 0x079f 1093#define mmRMI_SPARE_1_BASE_IDX 0 1094#define mmRMI_SPARE_2 0x07a0 1095#define mmRMI_SPARE_2_BASE_IDX 0 1096 1097 1098// addressBlock: gc_utcl2_atcl2dec 1099// base address: 0xa000 1100#define mmATC_L2_CNTL 0x0800 1101#define mmATC_L2_CNTL_BASE_IDX 0 1102#define mmATC_L2_CNTL2 0x0801 1103#define mmATC_L2_CNTL2_BASE_IDX 0 1104#define mmATC_L2_CACHE_DATA0 0x0804 1105#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 1106#define mmATC_L2_CACHE_DATA1 0x0805 1107#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 1108#define mmATC_L2_CACHE_DATA2 0x0806 1109#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 1110#define mmATC_L2_CNTL3 0x0807 1111#define mmATC_L2_CNTL3_BASE_IDX 0 1112#define mmATC_L2_STATUS 0x0808 1113#define mmATC_L2_STATUS_BASE_IDX 0 1114#define mmATC_L2_STATUS2 0x0809 1115#define mmATC_L2_STATUS2_BASE_IDX 0 1116#define mmATC_L2_MISC_CG 0x080a 1117#define mmATC_L2_MISC_CG_BASE_IDX 0 1118#define mmATC_L2_MEM_POWER_LS 0x080b 1119#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 1120#define mmATC_L2_CGTT_CLK_CTRL 0x080c 1121#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1122 1123 1124// addressBlock: gc_utcl2_vml2pfdec 1125// base address: 0xa100 1126#define mmVM_L2_CNTL 0x0840 1127#define mmVM_L2_CNTL_BASE_IDX 0 1128#define mmVM_L2_CNTL2 0x0841 1129#define mmVM_L2_CNTL2_BASE_IDX 0 1130#define mmVM_L2_CNTL3 0x0842 1131#define mmVM_L2_CNTL3_BASE_IDX 0 1132#define mmVM_L2_STATUS 0x0843 1133#define mmVM_L2_STATUS_BASE_IDX 0 1134#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844 1135#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1136#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 1137#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1138#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 1139#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1140#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847 1141#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1142#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848 1143#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1144#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 1145#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1146#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a 1147#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1148#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b 1149#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1150#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c 1151#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1152#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d 1153#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1154#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e 1155#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1156#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f 1157#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1158#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 1159#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1160#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 1161#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1162#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 1163#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1164#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 1165#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1166#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 1167#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1168#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 1169#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1170#define mmVM_L2_CNTL4 0x0857 1171#define mmVM_L2_CNTL4_BASE_IDX 0 1172#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858 1173#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1174#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859 1175#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1176#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a 1177#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1178#define mmVM_L2_CACHE_PARITY_CNTL 0x085b 1179#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1180#define mmVM_L2_CGTT_CLK_CTRL 0x085e 1181#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1182 1183 1184// addressBlock: gc_utcl2_vml2vcdec 1185// base address: 0xa200 1186#define mmVM_CONTEXT0_CNTL 0x0880 1187#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 1188#define mmVM_CONTEXT1_CNTL 0x0881 1189#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 1190#define mmVM_CONTEXT2_CNTL 0x0882 1191#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 1192#define mmVM_CONTEXT3_CNTL 0x0883 1193#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 1194#define mmVM_CONTEXT4_CNTL 0x0884 1195#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 1196#define mmVM_CONTEXT5_CNTL 0x0885 1197#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 1198#define mmVM_CONTEXT6_CNTL 0x0886 1199#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 1200#define mmVM_CONTEXT7_CNTL 0x0887 1201#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 1202#define mmVM_CONTEXT8_CNTL 0x0888 1203#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 1204#define mmVM_CONTEXT9_CNTL 0x0889 1205#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 1206#define mmVM_CONTEXT10_CNTL 0x088a 1207#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 1208#define mmVM_CONTEXT11_CNTL 0x088b 1209#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 1210#define mmVM_CONTEXT12_CNTL 0x088c 1211#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 1212#define mmVM_CONTEXT13_CNTL 0x088d 1213#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 1214#define mmVM_CONTEXT14_CNTL 0x088e 1215#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 1216#define mmVM_CONTEXT15_CNTL 0x088f 1217#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 1218#define mmVM_CONTEXTS_DISABLE 0x0890 1219#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 1220#define mmVM_INVALIDATE_ENG0_SEM 0x0891 1221#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1222#define mmVM_INVALIDATE_ENG1_SEM 0x0892 1223#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1224#define mmVM_INVALIDATE_ENG2_SEM 0x0893 1225#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1226#define mmVM_INVALIDATE_ENG3_SEM 0x0894 1227#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1228#define mmVM_INVALIDATE_ENG4_SEM 0x0895 1229#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1230#define mmVM_INVALIDATE_ENG5_SEM 0x0896 1231#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1232#define mmVM_INVALIDATE_ENG6_SEM 0x0897 1233#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1234#define mmVM_INVALIDATE_ENG7_SEM 0x0898 1235#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1236#define mmVM_INVALIDATE_ENG8_SEM 0x0899 1237#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1238#define mmVM_INVALIDATE_ENG9_SEM 0x089a 1239#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1240#define mmVM_INVALIDATE_ENG10_SEM 0x089b 1241#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1242#define mmVM_INVALIDATE_ENG11_SEM 0x089c 1243#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1244#define mmVM_INVALIDATE_ENG12_SEM 0x089d 1245#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1246#define mmVM_INVALIDATE_ENG13_SEM 0x089e 1247#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1248#define mmVM_INVALIDATE_ENG14_SEM 0x089f 1249#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1250#define mmVM_INVALIDATE_ENG15_SEM 0x08a0 1251#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1252#define mmVM_INVALIDATE_ENG16_SEM 0x08a1 1253#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1254#define mmVM_INVALIDATE_ENG17_SEM 0x08a2 1255#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1256#define mmVM_INVALIDATE_ENG0_REQ 0x08a3 1257#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1258#define mmVM_INVALIDATE_ENG1_REQ 0x08a4 1259#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1260#define mmVM_INVALIDATE_ENG2_REQ 0x08a5 1261#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1262#define mmVM_INVALIDATE_ENG3_REQ 0x08a6 1263#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1264#define mmVM_INVALIDATE_ENG4_REQ 0x08a7 1265#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1266#define mmVM_INVALIDATE_ENG5_REQ 0x08a8 1267#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1268#define mmVM_INVALIDATE_ENG6_REQ 0x08a9 1269#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1270#define mmVM_INVALIDATE_ENG7_REQ 0x08aa 1271#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1272#define mmVM_INVALIDATE_ENG8_REQ 0x08ab 1273#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1274#define mmVM_INVALIDATE_ENG9_REQ 0x08ac 1275#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1276#define mmVM_INVALIDATE_ENG10_REQ 0x08ad 1277#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1278#define mmVM_INVALIDATE_ENG11_REQ 0x08ae 1279#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1280#define mmVM_INVALIDATE_ENG12_REQ 0x08af 1281#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1282#define mmVM_INVALIDATE_ENG13_REQ 0x08b0 1283#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1284#define mmVM_INVALIDATE_ENG14_REQ 0x08b1 1285#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1286#define mmVM_INVALIDATE_ENG15_REQ 0x08b2 1287#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1288#define mmVM_INVALIDATE_ENG16_REQ 0x08b3 1289#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1290#define mmVM_INVALIDATE_ENG17_REQ 0x08b4 1291#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1292#define mmVM_INVALIDATE_ENG0_ACK 0x08b5 1293#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1294#define mmVM_INVALIDATE_ENG1_ACK 0x08b6 1295#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1296#define mmVM_INVALIDATE_ENG2_ACK 0x08b7 1297#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1298#define mmVM_INVALIDATE_ENG3_ACK 0x08b8 1299#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1300#define mmVM_INVALIDATE_ENG4_ACK 0x08b9 1301#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1302#define mmVM_INVALIDATE_ENG5_ACK 0x08ba 1303#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1304#define mmVM_INVALIDATE_ENG6_ACK 0x08bb 1305#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1306#define mmVM_INVALIDATE_ENG7_ACK 0x08bc 1307#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1308#define mmVM_INVALIDATE_ENG8_ACK 0x08bd 1309#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1310#define mmVM_INVALIDATE_ENG9_ACK 0x08be 1311#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1312#define mmVM_INVALIDATE_ENG10_ACK 0x08bf 1313#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1314#define mmVM_INVALIDATE_ENG11_ACK 0x08c0 1315#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1316#define mmVM_INVALIDATE_ENG12_ACK 0x08c1 1317#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1318#define mmVM_INVALIDATE_ENG13_ACK 0x08c2 1319#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1320#define mmVM_INVALIDATE_ENG14_ACK 0x08c3 1321#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1322#define mmVM_INVALIDATE_ENG15_ACK 0x08c4 1323#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1324#define mmVM_INVALIDATE_ENG16_ACK 0x08c5 1325#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1326#define mmVM_INVALIDATE_ENG17_ACK 0x08c6 1327#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1328#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 1329#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1330#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 1331#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1332#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 1333#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1334#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca 1335#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1336#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb 1337#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1338#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc 1339#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1340#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd 1341#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1342#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce 1343#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1344#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf 1345#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1346#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 1347#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1348#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 1349#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1350#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 1351#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1352#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 1353#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1354#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 1355#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1356#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 1357#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1358#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 1359#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1360#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 1361#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1362#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 1363#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1364#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 1365#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1366#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da 1367#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1368#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db 1369#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1370#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc 1371#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1372#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd 1373#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1374#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de 1375#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1376#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df 1377#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1378#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 1379#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1380#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 1381#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1382#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 1383#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1384#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 1385#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1386#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 1387#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1388#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 1389#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1390#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 1391#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1392#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 1393#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1394#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 1395#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1396#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 1397#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1398#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea 1399#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1400#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb 1401#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1402#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec 1403#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1404#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed 1405#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1406#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee 1407#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1408#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef 1409#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1410#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 1411#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1412#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 1413#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1414#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 1415#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1416#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 1417#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1418#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 1419#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1420#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 1421#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1422#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 1423#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1424#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 1425#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1426#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 1427#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1428#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 1429#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1430#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa 1431#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1432#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb 1433#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1434#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc 1435#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1436#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd 1437#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1438#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe 1439#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1440#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff 1441#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1442#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 1443#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1444#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 1445#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1446#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 1447#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1448#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 1449#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1450#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 1451#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1452#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 1453#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1454#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 1455#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1456#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 1457#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1458#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 1459#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1460#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 1461#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1462#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a 1463#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1464#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b 1465#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1466#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c 1467#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1468#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d 1469#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1470#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e 1471#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1472#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f 1473#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1474#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 1475#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1476#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 1477#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1478#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 1479#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1480#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 1481#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1482#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 1483#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1484#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 1485#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1486#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 1487#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1488#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 1489#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1490#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 1491#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1492#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 1493#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1494#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a 1495#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1496#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b 1497#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1498#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c 1499#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1500#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d 1501#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1502#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e 1503#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1504#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f 1505#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1506#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 1507#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1508#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 1509#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1510#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 1511#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1512#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 1513#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1514#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 1515#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1516#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 1517#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1518#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 1519#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1520#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 1521#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1522#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 1523#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1524#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 1525#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1526#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a 1527#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1528#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b 1529#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1530#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c 1531#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1532#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d 1533#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1534#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e 1535#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1536#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f 1537#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1538#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 1539#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1540#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 1541#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1542#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 1543#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1544#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 1545#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1546#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 1547#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1548#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 1549#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1550#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 1551#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1552#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 1553#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1554#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 1555#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1556#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 1557#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1558#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a 1559#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1560#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b 1561#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1562#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c 1563#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1564#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d 1565#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1566#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e 1567#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1568#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f 1569#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1570#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 1571#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1572#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 1573#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1574#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 1575#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1576#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 1577#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1578#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 1579#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1580#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 1581#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1582#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 1583#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1584#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 1585#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1586#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 1587#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1588#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 1589#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1590#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a 1591#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1592 1593 1594// addressBlock: gc_utcl2_vmsharedpfdec 1595// base address: 0xa590 1596#define mmMC_VM_NB_MMIOBASE 0x0964 1597#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 1598#define mmMC_VM_NB_MMIOLIMIT 0x0965 1599#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1600#define mmMC_VM_NB_PCI_CTRL 0x0966 1601#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 1602#define mmMC_VM_NB_PCI_ARB 0x0967 1603#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 1604#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968 1605#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1606#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969 1607#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1608#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a 1609#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1610#define mmMC_VM_FB_OFFSET 0x096b 1611#define mmMC_VM_FB_OFFSET_BASE_IDX 0 1612#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c 1613#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1614#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d 1615#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1616#define mmMC_VM_STEERING 0x096e 1617#define mmMC_VM_STEERING_BASE_IDX 0 1618#define mmMC_SHARED_VIRT_RESET_REQ 0x096f 1619#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1620#define mmMC_MEM_POWER_LS 0x0970 1621#define mmMC_MEM_POWER_LS_BASE_IDX 0 1622#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 1623#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1624#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 1625#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1626#define mmMC_VM_APT_CNTL 0x0973 1627#define mmMC_VM_APT_CNTL_BASE_IDX 0 1628#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 1629#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1630#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 1631#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1632#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 1633#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1634#define mmMC_VM_XGMI_LFB_CNTL 0x0977 1635#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 1636#define mmMC_VM_XGMI_LFB_SIZE 0x0978 1637#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 1638 1639 1640// addressBlock: gc_utcl2_vmsharedvcdec 1641// base address: 0xa600 1642#define mmMC_VM_FB_LOCATION_BASE 0x0980 1643#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1644#define mmMC_VM_FB_LOCATION_TOP 0x0981 1645#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1646#define mmMC_VM_AGP_TOP 0x0982 1647#define mmMC_VM_AGP_TOP_BASE_IDX 0 1648#define mmMC_VM_AGP_BOT 0x0983 1649#define mmMC_VM_AGP_BOT_BASE_IDX 0 1650#define mmMC_VM_AGP_BASE 0x0984 1651#define mmMC_VM_AGP_BASE_BASE_IDX 0 1652#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 1653#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1654#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 1655#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1656#define mmMC_VM_MX_L1_TLB_CNTL 0x0987 1657#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1658 1659 1660// addressBlock: gc_ea_gceadec 1661// base address: 0xa800 1662#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 1663#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1664#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 1665#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1666#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 1667#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1668#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 1669#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1670#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 1671#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1672#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 1673#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1674#define mmGCEA_DRAM_RD_LAZY 0x0a06 1675#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0 1676#define mmGCEA_DRAM_WR_LAZY 0x0a07 1677#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0 1678#define mmGCEA_DRAM_RD_CAM_CNTL 0x0a08 1679#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 1680#define mmGCEA_DRAM_WR_CAM_CNTL 0x0a09 1681#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 1682#define mmGCEA_DRAM_PAGE_BURST 0x0a0a 1683#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0 1684#define mmGCEA_DRAM_RD_PRI_AGE 0x0a0b 1685#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 1686#define mmGCEA_DRAM_WR_PRI_AGE 0x0a0c 1687#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 1688#define mmGCEA_DRAM_RD_PRI_QUEUING 0x0a0d 1689#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1690#define mmGCEA_DRAM_WR_PRI_QUEUING 0x0a0e 1691#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1692#define mmGCEA_DRAM_RD_PRI_FIXED 0x0a0f 1693#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 1694#define mmGCEA_DRAM_WR_PRI_FIXED 0x0a10 1695#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 1696#define mmGCEA_DRAM_RD_PRI_URGENCY 0x0a11 1697#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1698#define mmGCEA_DRAM_WR_PRI_URGENCY 0x0a12 1699#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1700#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 1701#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1702#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 1703#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1704#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 1705#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1706#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 1707#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1708#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 1709#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1710#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 1711#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1712#define mmGCEA_ADDRNORM_BASE_ADDR0 0x0a34 1713#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 1714#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x0a35 1715#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 1716#define mmGCEA_ADDRNORM_BASE_ADDR1 0x0a36 1717#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 1718#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x0a37 1719#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 1720#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x0a38 1721#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 1722#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL 0x0a43 1723#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 1724#define mmGCEA_ADDRNORMDRAM_TRICHANNEL_CFG 0x0a45 1725#define mmGCEA_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0 1726#define mmGCEA_ADDRDEC_BANK_CFG 0x0a47 1727#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 1728#define mmGCEA_ADDRDEC_MISC_CFG 0x0a48 1729#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 1730#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x0a49 1731#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 1732#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x0a4a 1733#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 1734#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x0a4b 1735#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 1736#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x0a4c 1737#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 1738#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x0a4d 1739#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 1740#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x0a4e 1741#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 1742#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x0a4f 1743#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 1744#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x0a50 1745#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 1746#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x0a51 1747#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 1748#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a52 1749#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 1750#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a5d 1751#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 1752#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a5e 1753#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 1754#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a5f 1755#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 1756#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a60 1757#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 1758#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a61 1759#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 1760#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a62 1761#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 1762#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a63 1763#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 1764#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a64 1765#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 1766#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a65 1767#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 1768#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a66 1769#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 1770#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a67 1771#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 1772#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a68 1773#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 1774#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a69 1775#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 1776#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a6a 1777#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 1778#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a6b 1779#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 1780#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a6c 1781#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 1782#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a6d 1783#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 1784#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a6e 1785#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 1786#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a6f 1787#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 1788#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a70 1789#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 1790#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x0a71 1791#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 1792#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x0a72 1793#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 1794#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a73 1795#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 1796#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a74 1797#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 1798#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a75 1799#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 1800#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a76 1801#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 1802#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a77 1803#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 1804#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a78 1805#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 1806#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a79 1807#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 1808#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a7a 1809#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 1810#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a7b 1811#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 1812#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a7c 1813#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 1814#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a7d 1815#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 1816#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a7e 1817#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 1818#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a7f 1819#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 1820#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a80 1821#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 1822#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a81 1823#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 1824#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a82 1825#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 1826#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a83 1827#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 1828#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a84 1829#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 1830#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a85 1831#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 1832#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a86 1833#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 1834#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a87 1835#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 1836#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a88 1837#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 1838#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x0a89 1839#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 1840#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x0a8a 1841#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 1842#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a8b 1843#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 1844#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a8c 1845#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 1846#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 1847#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1848#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 1849#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1850#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 1851#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1852#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 1853#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1854#define mmGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 1855#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1856#define mmGCEA_IO_WR_COMBINE_FLUSH 0x0ada 1857#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1858#define mmGCEA_IO_GROUP_BURST 0x0adb 1859#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0 1860#define mmGCEA_IO_RD_PRI_AGE 0x0adc 1861#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0 1862#define mmGCEA_IO_WR_PRI_AGE 0x0add 1863#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0 1864#define mmGCEA_IO_RD_PRI_QUEUING 0x0ade 1865#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 1866#define mmGCEA_IO_WR_PRI_QUEUING 0x0adf 1867#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 1868#define mmGCEA_IO_RD_PRI_FIXED 0x0ae0 1869#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 1870#define mmGCEA_IO_WR_PRI_FIXED 0x0ae1 1871#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 1872#define mmGCEA_IO_RD_PRI_URGENCY 0x0ae2 1873#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 1874#define mmGCEA_IO_WR_PRI_URGENCY 0x0ae3 1875#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 1876#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x0ae4 1877#define mmGCEA_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 1878#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x0ae5 1879#define mmGCEA_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 1880#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 1881#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1882#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 1883#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1884#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 1885#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1886#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 1887#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1888#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea 1889#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1890#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb 1891#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1892#define mmGCEA_SDP_ARB_DRAM 0x0aec 1893#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0 1894#define mmGCEA_SDP_ARB_FINAL 0x0aee 1895#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0 1896#define mmGCEA_SDP_DRAM_PRIORITY 0x0aef 1897#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 1898#define mmGCEA_SDP_IO_PRIORITY 0x0af1 1899#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0 1900#define mmGCEA_SDP_CREDITS 0x0af2 1901#define mmGCEA_SDP_CREDITS_BASE_IDX 0 1902#define mmGCEA_SDP_TAG_RESERVE0 0x0af3 1903#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 1904#define mmGCEA_SDP_TAG_RESERVE1 0x0af4 1905#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 1906#define mmGCEA_SDP_VCC_RESERVE0 0x0af5 1907#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 1908#define mmGCEA_SDP_VCC_RESERVE1 0x0af6 1909#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 1910#define mmGCEA_SDP_VCD_RESERVE0 0x0af7 1911#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 1912#define mmGCEA_SDP_VCD_RESERVE1 0x0af8 1913#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 1914#define mmGCEA_SDP_REQ_CNTL 0x0af9 1915#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0 1916#define mmGCEA_MISC 0x0afa 1917#define mmGCEA_MISC_BASE_IDX 0 1918#define mmGCEA_LATENCY_SAMPLING 0x0afb 1919#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0 1920#define mmGCEA_PERFCOUNTER_LO 0x0afc 1921#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0 1922#define mmGCEA_PERFCOUNTER_HI 0x0afd 1923#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0 1924#define mmGCEA_PERFCOUNTER0_CFG 0x0afe 1925#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 1926#define mmGCEA_PERFCOUNTER1_CFG 0x0aff 1927#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 1928 1929 1930// addressBlock: gc_tcdec 1931// base address: 0xac00 1932#define mmTCP_INVALIDATE 0x0b00 1933#define mmTCP_INVALIDATE_BASE_IDX 0 1934#define mmTCP_STATUS 0x0b01 1935#define mmTCP_STATUS_BASE_IDX 0 1936#define mmTCP_CNTL 0x0b02 1937#define mmTCP_CNTL_BASE_IDX 0 1938#define mmTCP_CHAN_STEER_LO 0x0b03 1939#define mmTCP_CHAN_STEER_LO_BASE_IDX 0 1940#define mmTCP_CHAN_STEER_HI 0x0b04 1941#define mmTCP_CHAN_STEER_HI_BASE_IDX 0 1942#define mmTCP_ADDR_CONFIG 0x0b05 1943#define mmTCP_ADDR_CONFIG_BASE_IDX 0 1944#define mmTCP_CREDIT 0x0b06 1945#define mmTCP_CREDIT_BASE_IDX 0 1946#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 1947#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 1948#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a 1949#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 1950#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b 1951#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 1952#define mmTC_CFG_L1_STORE_POLICY 0x0b1c 1953#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0 1954#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d 1955#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 1956#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e 1957#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 1958#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f 1959#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 1960#define mmTC_CFG_L2_STORE_POLICY1 0x0b20 1961#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 1962#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21 1963#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 1964#define mmTC_CFG_L1_VOLATILE 0x0b22 1965#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0 1966#define mmTC_CFG_L2_VOLATILE 0x0b23 1967#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0 1968#define mmTCI_STATUS 0x0b61 1969#define mmTCI_STATUS_BASE_IDX 0 1970#define mmTCI_CNTL_1 0x0b62 1971#define mmTCI_CNTL_1_BASE_IDX 0 1972#define mmTCI_CNTL_2 0x0b63 1973#define mmTCI_CNTL_2_BASE_IDX 0 1974#define mmTCC_CTRL 0x0b80 1975#define mmTCC_CTRL_BASE_IDX 0 1976#define mmTCC_CTRL2 0x0b81 1977#define mmTCC_CTRL2_BASE_IDX 0 1978#define mmTCC_REDUNDANCY 0x0b84 1979#define mmTCC_REDUNDANCY_BASE_IDX 0 1980#define mmTCC_EXE_DISABLE 0x0b85 1981#define mmTCC_EXE_DISABLE_BASE_IDX 0 1982#define mmTCC_DSM_CNTL 0x0b86 1983#define mmTCC_DSM_CNTL_BASE_IDX 0 1984#define mmTCC_DSM_CNTLA 0x0b87 1985#define mmTCC_DSM_CNTLA_BASE_IDX 0 1986#define mmTCC_DSM_CNTL2 0x0b88 1987#define mmTCC_DSM_CNTL2_BASE_IDX 0 1988#define mmTCC_DSM_CNTL2A 0x0b89 1989#define mmTCC_DSM_CNTL2A_BASE_IDX 0 1990#define mmTCC_DSM_CNTL2B 0x0b8a 1991#define mmTCC_DSM_CNTL2B_BASE_IDX 0 1992#define mmTCC_WBINVL2 0x0b8b 1993#define mmTCC_WBINVL2_BASE_IDX 0 1994#define mmTCC_SOFT_RESET 0x0b8c 1995#define mmTCC_SOFT_RESET_BASE_IDX 0 1996#define mmTCA_CTRL 0x0bc0 1997#define mmTCA_CTRL_BASE_IDX 0 1998#define mmTCA_BURST_MASK 0x0bc1 1999#define mmTCA_BURST_MASK_BASE_IDX 0 2000#define mmTCA_BURST_CTRL 0x0bc2 2001#define mmTCA_BURST_CTRL_BASE_IDX 0 2002#define mmTCA_DSM_CNTL 0x0bc3 2003#define mmTCA_DSM_CNTL_BASE_IDX 0 2004#define mmTCA_DSM_CNTL2 0x0bc4 2005#define mmTCA_DSM_CNTL2_BASE_IDX 0 2006 2007 2008// addressBlock: gc_shdec 2009// base address: 0xb000 2010#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07 2011#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 2012#define mmSPI_SHADER_PGM_LO_PS 0x0c08 2013#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 2014#define mmSPI_SHADER_PGM_HI_PS 0x0c09 2015#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 2016#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a 2017#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 2018#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b 2019#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 2020#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c 2021#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 2022#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d 2023#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 2024#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e 2025#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 2026#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f 2027#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 2028#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10 2029#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 2030#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11 2031#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 2032#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12 2033#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 2034#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13 2035#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 2036#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14 2037#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 2038#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15 2039#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 2040#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16 2041#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 2042#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17 2043#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 2044#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18 2045#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 2046#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19 2047#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 2048#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a 2049#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 2050#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b 2051#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 2052#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c 2053#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 2054#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d 2055#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 2056#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e 2057#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 2058#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f 2059#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 2060#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20 2061#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 2062#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21 2063#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 2064#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22 2065#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 2066#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23 2067#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 2068#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24 2069#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 2070#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25 2071#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 2072#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26 2073#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 2074#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27 2075#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 2076#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28 2077#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 2078#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29 2079#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 2080#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a 2081#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 2082#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b 2083#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 2084#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46 2085#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 2086#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47 2087#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 2088#define mmSPI_SHADER_PGM_LO_VS 0x0c48 2089#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 2090#define mmSPI_SHADER_PGM_HI_VS 0x0c49 2091#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 2092#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a 2093#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 2094#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b 2095#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 2096#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c 2097#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 2098#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d 2099#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 2100#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e 2101#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 2102#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f 2103#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 2104#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50 2105#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 2106#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51 2107#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 2108#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52 2109#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 2110#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53 2111#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 2112#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54 2113#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 2114#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55 2115#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 2116#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56 2117#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 2118#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57 2119#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 2120#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58 2121#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 2122#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59 2123#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 2124#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a 2125#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 2126#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b 2127#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 2128#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c 2129#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 2130#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d 2131#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 2132#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e 2133#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 2134#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f 2135#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 2136#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60 2137#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 2138#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61 2139#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 2140#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62 2141#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 2142#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63 2143#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 2144#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64 2145#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 2146#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65 2147#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 2148#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66 2149#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 2150#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67 2151#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 2152#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68 2153#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 2154#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69 2155#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 2156#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a 2157#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 2158#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b 2159#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 2160#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c 2161#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 2162#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81 2163#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 2164#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 2165#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 2166#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 2167#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 2168#define mmSPI_SHADER_PGM_LO_ES 0x0c84 2169#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 2170#define mmSPI_SHADER_PGM_HI_ES 0x0c85 2171#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 2172#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87 2173#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 2174#define mmSPI_SHADER_PGM_LO_GS 0x0c88 2175#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 2176#define mmSPI_SHADER_PGM_HI_GS 0x0c89 2177#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 2178#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a 2179#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 2180#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b 2181#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 2182#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc 2183#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 2184#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd 2185#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 2186#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce 2187#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 2188#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf 2189#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 2190#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0 2191#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 2192#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1 2193#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 2194#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2 2195#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 2196#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3 2197#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 2198#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4 2199#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 2200#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5 2201#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 2202#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6 2203#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 2204#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7 2205#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 2206#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8 2207#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 2208#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9 2209#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 2210#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda 2211#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 2212#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb 2213#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 2214#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc 2215#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 2216#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd 2217#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 2218#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde 2219#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 2220#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf 2221#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 2222#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0 2223#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 2224#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1 2225#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 2226#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2 2227#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 2228#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3 2229#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 2230#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4 2231#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 2232#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5 2233#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 2234#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6 2235#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 2236#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7 2237#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 2238#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8 2239#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 2240#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9 2241#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 2242#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea 2243#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 2244#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb 2245#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 2246#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01 2247#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 2248#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 2249#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 2250#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 2251#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 2252#define mmSPI_SHADER_PGM_LO_LS 0x0d04 2253#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 2254#define mmSPI_SHADER_PGM_HI_LS 0x0d05 2255#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 2256#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07 2257#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 2258#define mmSPI_SHADER_PGM_LO_HS 0x0d08 2259#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 2260#define mmSPI_SHADER_PGM_HI_HS 0x0d09 2261#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 2262#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a 2263#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 2264#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b 2265#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 2266#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c 2267#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 2268#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d 2269#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 2270#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e 2271#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 2272#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f 2273#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 2274#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10 2275#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 2276#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11 2277#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 2278#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12 2279#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 2280#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13 2281#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 2282#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14 2283#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 2284#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15 2285#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 2286#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16 2287#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 2288#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17 2289#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 2290#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18 2291#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 2292#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19 2293#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 2294#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a 2295#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 2296#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b 2297#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 2298#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c 2299#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 2300#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d 2301#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 2302#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e 2303#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 2304#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f 2305#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 2306#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20 2307#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 2308#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21 2309#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 2310#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22 2311#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 2312#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23 2313#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 2314#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24 2315#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 2316#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25 2317#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 2318#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26 2319#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 2320#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27 2321#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 2322#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28 2323#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 2324#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29 2325#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 2326#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a 2327#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 2328#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b 2329#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 2330#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c 2331#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 2332#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d 2333#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 2334#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e 2335#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 2336#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f 2337#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 2338#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50 2339#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 2340#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51 2341#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 2342#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52 2343#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 2344#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53 2345#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 2346#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54 2347#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 2348#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55 2349#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 2350#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56 2351#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 2352#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57 2353#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 2354#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58 2355#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 2356#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59 2357#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 2358#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a 2359#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 2360#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b 2361#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 2362#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c 2363#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 2364#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d 2365#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 2366#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e 2367#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 2368#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f 2369#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 2370#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60 2371#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 2372#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61 2373#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 2374#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62 2375#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 2376#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63 2377#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 2378#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64 2379#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 2380#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65 2381#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 2382#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66 2383#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 2384#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67 2385#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 2386#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68 2387#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 2388#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69 2389#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 2390#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a 2391#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 2392#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b 2393#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 2394#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00 2395#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 2396#define mmCOMPUTE_DIM_X 0x0e01 2397#define mmCOMPUTE_DIM_X_BASE_IDX 0 2398#define mmCOMPUTE_DIM_Y 0x0e02 2399#define mmCOMPUTE_DIM_Y_BASE_IDX 0 2400#define mmCOMPUTE_DIM_Z 0x0e03 2401#define mmCOMPUTE_DIM_Z_BASE_IDX 0 2402#define mmCOMPUTE_START_X 0x0e04 2403#define mmCOMPUTE_START_X_BASE_IDX 0 2404#define mmCOMPUTE_START_Y 0x0e05 2405#define mmCOMPUTE_START_Y_BASE_IDX 0 2406#define mmCOMPUTE_START_Z 0x0e06 2407#define mmCOMPUTE_START_Z_BASE_IDX 0 2408#define mmCOMPUTE_NUM_THREAD_X 0x0e07 2409#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 2410#define mmCOMPUTE_NUM_THREAD_Y 0x0e08 2411#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 2412#define mmCOMPUTE_NUM_THREAD_Z 0x0e09 2413#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 2414#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a 2415#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 2416#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b 2417#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 2418#define mmCOMPUTE_PGM_LO 0x0e0c 2419#define mmCOMPUTE_PGM_LO_BASE_IDX 0 2420#define mmCOMPUTE_PGM_HI 0x0e0d 2421#define mmCOMPUTE_PGM_HI_BASE_IDX 0 2422#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e 2423#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 2424#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f 2425#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 2426#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 2427#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 2428#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 2429#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 2430#define mmCOMPUTE_PGM_RSRC1 0x0e12 2431#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 2432#define mmCOMPUTE_PGM_RSRC2 0x0e13 2433#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 2434#define mmCOMPUTE_VMID 0x0e14 2435#define mmCOMPUTE_VMID_BASE_IDX 0 2436#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15 2437#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 2438#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 2439#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 2440#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 2441#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 2442#define mmCOMPUTE_TMPRING_SIZE 0x0e18 2443#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 2444#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 2445#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 2446#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a 2447#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 2448#define mmCOMPUTE_RESTART_X 0x0e1b 2449#define mmCOMPUTE_RESTART_X_BASE_IDX 0 2450#define mmCOMPUTE_RESTART_Y 0x0e1c 2451#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 2452#define mmCOMPUTE_RESTART_Z 0x0e1d 2453#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 2454#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e 2455#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 2456#define mmCOMPUTE_MISC_RESERVED 0x0e1f 2457#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 2458#define mmCOMPUTE_DISPATCH_ID 0x0e20 2459#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 2460#define mmCOMPUTE_THREADGROUP_ID 0x0e21 2461#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 2462#define mmCOMPUTE_RELAUNCH 0x0e22 2463#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 2464#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 2465#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 2466#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 2467#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 2468#define mmCOMPUTE_SHADER_CHKSUM 0x0e25 2469#define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 2470#define mmCOMPUTE_USER_DATA_0 0x0e40 2471#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 2472#define mmCOMPUTE_USER_DATA_1 0x0e41 2473#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 2474#define mmCOMPUTE_USER_DATA_2 0x0e42 2475#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 2476#define mmCOMPUTE_USER_DATA_3 0x0e43 2477#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 2478#define mmCOMPUTE_USER_DATA_4 0x0e44 2479#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 2480#define mmCOMPUTE_USER_DATA_5 0x0e45 2481#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 2482#define mmCOMPUTE_USER_DATA_6 0x0e46 2483#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 2484#define mmCOMPUTE_USER_DATA_7 0x0e47 2485#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 2486#define mmCOMPUTE_USER_DATA_8 0x0e48 2487#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 2488#define mmCOMPUTE_USER_DATA_9 0x0e49 2489#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 2490#define mmCOMPUTE_USER_DATA_10 0x0e4a 2491#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 2492#define mmCOMPUTE_USER_DATA_11 0x0e4b 2493#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 2494#define mmCOMPUTE_USER_DATA_12 0x0e4c 2495#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 2496#define mmCOMPUTE_USER_DATA_13 0x0e4d 2497#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 2498#define mmCOMPUTE_USER_DATA_14 0x0e4e 2499#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 2500#define mmCOMPUTE_USER_DATA_15 0x0e4f 2501#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 2502#define mmCOMPUTE_DISPATCH_END 0x0e7e 2503#define mmCOMPUTE_DISPATCH_END_BASE_IDX 0 2504#define mmCOMPUTE_NOWHERE 0x0e7f 2505#define mmCOMPUTE_NOWHERE_BASE_IDX 0 2506 2507 2508// addressBlock: gc_cppdec 2509// base address: 0xc080 2510#define mmCP_DFY_CNTL 0x1020 2511#define mmCP_DFY_CNTL_BASE_IDX 0 2512#define mmCP_DFY_STAT 0x1021 2513#define mmCP_DFY_STAT_BASE_IDX 0 2514#define mmCP_DFY_ADDR_HI 0x1022 2515#define mmCP_DFY_ADDR_HI_BASE_IDX 0 2516#define mmCP_DFY_ADDR_LO 0x1023 2517#define mmCP_DFY_ADDR_LO_BASE_IDX 0 2518#define mmCP_DFY_DATA_0 0x1024 2519#define mmCP_DFY_DATA_0_BASE_IDX 0 2520#define mmCP_DFY_DATA_1 0x1025 2521#define mmCP_DFY_DATA_1_BASE_IDX 0 2522#define mmCP_DFY_DATA_2 0x1026 2523#define mmCP_DFY_DATA_2_BASE_IDX 0 2524#define mmCP_DFY_DATA_3 0x1027 2525#define mmCP_DFY_DATA_3_BASE_IDX 0 2526#define mmCP_DFY_DATA_4 0x1028 2527#define mmCP_DFY_DATA_4_BASE_IDX 0 2528#define mmCP_DFY_DATA_5 0x1029 2529#define mmCP_DFY_DATA_5_BASE_IDX 0 2530#define mmCP_DFY_DATA_6 0x102a 2531#define mmCP_DFY_DATA_6_BASE_IDX 0 2532#define mmCP_DFY_DATA_7 0x102b 2533#define mmCP_DFY_DATA_7_BASE_IDX 0 2534#define mmCP_DFY_DATA_8 0x102c 2535#define mmCP_DFY_DATA_8_BASE_IDX 0 2536#define mmCP_DFY_DATA_9 0x102d 2537#define mmCP_DFY_DATA_9_BASE_IDX 0 2538#define mmCP_DFY_DATA_10 0x102e 2539#define mmCP_DFY_DATA_10_BASE_IDX 0 2540#define mmCP_DFY_DATA_11 0x102f 2541#define mmCP_DFY_DATA_11_BASE_IDX 0 2542#define mmCP_DFY_DATA_12 0x1030 2543#define mmCP_DFY_DATA_12_BASE_IDX 0 2544#define mmCP_DFY_DATA_13 0x1031 2545#define mmCP_DFY_DATA_13_BASE_IDX 0 2546#define mmCP_DFY_DATA_14 0x1032 2547#define mmCP_DFY_DATA_14_BASE_IDX 0 2548#define mmCP_DFY_DATA_15 0x1033 2549#define mmCP_DFY_DATA_15_BASE_IDX 0 2550#define mmCP_DFY_CMD 0x1034 2551#define mmCP_DFY_CMD_BASE_IDX 0 2552#define mmCP_EOPQ_WAIT_TIME 0x1035 2553#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 2554#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036 2555#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 2556#define mmCPC_INT_INFO 0x1037 2557#define mmCPC_INT_INFO_BASE_IDX 0 2558#define mmCP_VIRT_STATUS 0x1038 2559#define mmCP_VIRT_STATUS_BASE_IDX 0 2560#define mmCPC_INT_ADDR 0x1039 2561#define mmCPC_INT_ADDR_BASE_IDX 0 2562#define mmCPC_INT_PASID 0x103a 2563#define mmCPC_INT_PASID_BASE_IDX 0 2564#define mmCP_GFX_ERROR 0x103b 2565#define mmCP_GFX_ERROR_BASE_IDX 0 2566#define mmCPG_UTCL1_CNTL 0x103c 2567#define mmCPG_UTCL1_CNTL_BASE_IDX 0 2568#define mmCPC_UTCL1_CNTL 0x103d 2569#define mmCPC_UTCL1_CNTL_BASE_IDX 0 2570#define mmCPF_UTCL1_CNTL 0x103e 2571#define mmCPF_UTCL1_CNTL_BASE_IDX 0 2572#define mmCP_AQL_SMM_STATUS 0x103f 2573#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 2574#define mmCP_RB0_BASE 0x1040 2575#define mmCP_RB0_BASE_BASE_IDX 0 2576#define mmCP_RB_BASE 0x1040 2577#define mmCP_RB_BASE_BASE_IDX 0 2578#define mmCP_RB0_CNTL 0x1041 2579#define mmCP_RB0_CNTL_BASE_IDX 0 2580#define mmCP_RB_CNTL 0x1041 2581#define mmCP_RB_CNTL_BASE_IDX 0 2582#define mmCP_RB_RPTR_WR 0x1042 2583#define mmCP_RB_RPTR_WR_BASE_IDX 0 2584#define mmCP_RB0_RPTR_ADDR 0x1043 2585#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 2586#define mmCP_RB_RPTR_ADDR 0x1043 2587#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 2588#define mmCP_RB0_RPTR_ADDR_HI 0x1044 2589#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 2590#define mmCP_RB_RPTR_ADDR_HI 0x1044 2591#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 2592#define mmCP_RB0_BUFSZ_MASK 0x1045 2593#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 2594#define mmCP_RB_BUFSZ_MASK 0x1045 2595#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 2596#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 2597#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 2598#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 2599#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 2600#define mmGC_PRIV_MODE 0x1048 2601#define mmGC_PRIV_MODE_BASE_IDX 0 2602#define mmCP_INT_CNTL 0x1049 2603#define mmCP_INT_CNTL_BASE_IDX 0 2604#define mmCP_INT_STATUS 0x104a 2605#define mmCP_INT_STATUS_BASE_IDX 0 2606#define mmCP_DEVICE_ID 0x104b 2607#define mmCP_DEVICE_ID_BASE_IDX 0 2608#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c 2609#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 2610#define mmCP_RING_PRIORITY_CNTS 0x104c 2611#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 2612#define mmCP_ME0_PIPE0_PRIORITY 0x104d 2613#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 2614#define mmCP_RING0_PRIORITY 0x104d 2615#define mmCP_RING0_PRIORITY_BASE_IDX 0 2616#define mmCP_ME0_PIPE1_PRIORITY 0x104e 2617#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 2618#define mmCP_RING1_PRIORITY 0x104e 2619#define mmCP_RING1_PRIORITY_BASE_IDX 0 2620#define mmCP_ME0_PIPE2_PRIORITY 0x104f 2621#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 2622#define mmCP_RING2_PRIORITY 0x104f 2623#define mmCP_RING2_PRIORITY_BASE_IDX 0 2624#define mmCP_FATAL_ERROR 0x1050 2625#define mmCP_FATAL_ERROR_BASE_IDX 0 2626#define mmCP_RB_VMID 0x1051 2627#define mmCP_RB_VMID_BASE_IDX 0 2628#define mmCP_ME0_PIPE0_VMID 0x1052 2629#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 2630#define mmCP_ME0_PIPE1_VMID 0x1053 2631#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 2632#define mmCP_RB0_WPTR 0x1054 2633#define mmCP_RB0_WPTR_BASE_IDX 0 2634#define mmCP_RB_WPTR 0x1054 2635#define mmCP_RB_WPTR_BASE_IDX 0 2636#define mmCP_RB0_WPTR_HI 0x1055 2637#define mmCP_RB0_WPTR_HI_BASE_IDX 0 2638#define mmCP_RB_WPTR_HI 0x1055 2639#define mmCP_RB_WPTR_HI_BASE_IDX 0 2640#define mmCP_RB1_WPTR 0x1056 2641#define mmCP_RB1_WPTR_BASE_IDX 0 2642#define mmCP_RB1_WPTR_HI 0x1057 2643#define mmCP_RB1_WPTR_HI_BASE_IDX 0 2644#define mmCP_RB2_WPTR 0x1058 2645#define mmCP_RB2_WPTR_BASE_IDX 0 2646#define mmCP_RB_DOORBELL_CONTROL 0x1059 2647#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 2648#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a 2649#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 2650#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b 2651#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 2652#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c 2653#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 2654#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d 2655#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 2656#define mmCPG_UTCL1_ERROR 0x105e 2657#define mmCPG_UTCL1_ERROR_BASE_IDX 0 2658#define mmCPC_UTCL1_ERROR 0x105f 2659#define mmCPC_UTCL1_ERROR_BASE_IDX 0 2660#define mmCP_RB1_BASE 0x1060 2661#define mmCP_RB1_BASE_BASE_IDX 0 2662#define mmCP_RB1_CNTL 0x1061 2663#define mmCP_RB1_CNTL_BASE_IDX 0 2664#define mmCP_RB1_RPTR_ADDR 0x1062 2665#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 2666#define mmCP_RB1_RPTR_ADDR_HI 0x1063 2667#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 2668#define mmCP_RB2_BASE 0x1065 2669#define mmCP_RB2_BASE_BASE_IDX 0 2670#define mmCP_RB2_CNTL 0x1066 2671#define mmCP_RB2_CNTL_BASE_IDX 0 2672#define mmCP_RB2_RPTR_ADDR 0x1067 2673#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 2674#define mmCP_RB2_RPTR_ADDR_HI 0x1068 2675#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 2676#define mmCP_RB0_ACTIVE 0x1069 2677#define mmCP_RB0_ACTIVE_BASE_IDX 0 2678#define mmCP_RB_ACTIVE 0x1069 2679#define mmCP_RB_ACTIVE_BASE_IDX 0 2680#define mmCP_INT_CNTL_RING0 0x106a 2681#define mmCP_INT_CNTL_RING0_BASE_IDX 0 2682#define mmCP_INT_CNTL_RING1 0x106b 2683#define mmCP_INT_CNTL_RING1_BASE_IDX 0 2684#define mmCP_INT_CNTL_RING2 0x106c 2685#define mmCP_INT_CNTL_RING2_BASE_IDX 0 2686#define mmCP_INT_STATUS_RING0 0x106d 2687#define mmCP_INT_STATUS_RING0_BASE_IDX 0 2688#define mmCP_INT_STATUS_RING1 0x106e 2689#define mmCP_INT_STATUS_RING1_BASE_IDX 0 2690#define mmCP_INT_STATUS_RING2 0x106f 2691#define mmCP_INT_STATUS_RING2_BASE_IDX 0 2692#define mmCP_PWR_CNTL 0x1078 2693#define mmCP_PWR_CNTL_BASE_IDX 0 2694#define mmCP_MEM_SLP_CNTL 0x1079 2695#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 2696#define mmCP_ECC_FIRSTOCCURRENCE 0x107a 2697#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 2698#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b 2699#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 2700#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c 2701#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 2702#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d 2703#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 2704#define mmCP_PQ_WPTR_POLL_CNTL 0x1083 2705#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 2706#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084 2707#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 2708#define mmCP_ME1_PIPE0_INT_CNTL 0x1085 2709#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 2710#define mmCP_ME1_PIPE1_INT_CNTL 0x1086 2711#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 2712#define mmCP_ME1_PIPE2_INT_CNTL 0x1087 2713#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 2714#define mmCP_ME1_PIPE3_INT_CNTL 0x1088 2715#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 2716#define mmCP_ME2_PIPE0_INT_CNTL 0x1089 2717#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 2718#define mmCP_ME2_PIPE1_INT_CNTL 0x108a 2719#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 2720#define mmCP_ME2_PIPE2_INT_CNTL 0x108b 2721#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 2722#define mmCP_ME2_PIPE3_INT_CNTL 0x108c 2723#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 2724#define mmCP_ME1_PIPE0_INT_STATUS 0x108d 2725#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 2726#define mmCP_ME1_PIPE1_INT_STATUS 0x108e 2727#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 2728#define mmCP_ME1_PIPE2_INT_STATUS 0x108f 2729#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 2730#define mmCP_ME1_PIPE3_INT_STATUS 0x1090 2731#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 2732#define mmCP_ME2_PIPE0_INT_STATUS 0x1091 2733#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 2734#define mmCP_ME2_PIPE1_INT_STATUS 0x1092 2735#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 2736#define mmCP_ME2_PIPE2_INT_STATUS 0x1093 2737#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 2738#define mmCP_ME2_PIPE3_INT_STATUS 0x1094 2739#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 2740#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099 2741#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 2742#define mmCP_ME1_PIPE0_PRIORITY 0x109a 2743#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 2744#define mmCP_ME1_PIPE1_PRIORITY 0x109b 2745#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 2746#define mmCP_ME1_PIPE2_PRIORITY 0x109c 2747#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 2748#define mmCP_ME1_PIPE3_PRIORITY 0x109d 2749#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 2750#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e 2751#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 2752#define mmCP_ME2_PIPE0_PRIORITY 0x109f 2753#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 2754#define mmCP_ME2_PIPE1_PRIORITY 0x10a0 2755#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 2756#define mmCP_ME2_PIPE2_PRIORITY 0x10a1 2757#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 2758#define mmCP_ME2_PIPE3_PRIORITY 0x10a2 2759#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 2760#define mmCP_CE_PRGRM_CNTR_START 0x10a3 2761#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 2762#define mmCP_PFP_PRGRM_CNTR_START 0x10a4 2763#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 2764#define mmCP_ME_PRGRM_CNTR_START 0x10a5 2765#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 2766#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6 2767#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 2768#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7 2769#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 2770#define mmCP_CE_INTR_ROUTINE_START 0x10a8 2771#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 2772#define mmCP_PFP_INTR_ROUTINE_START 0x10a9 2773#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 2774#define mmCP_ME_INTR_ROUTINE_START 0x10aa 2775#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 2776#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab 2777#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 2778#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac 2779#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 2780#define mmCP_CONTEXT_CNTL 0x10ad 2781#define mmCP_CONTEXT_CNTL_BASE_IDX 0 2782#define mmCP_MAX_CONTEXT 0x10ae 2783#define mmCP_MAX_CONTEXT_BASE_IDX 0 2784#define mmCP_IQ_WAIT_TIME1 0x10af 2785#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 2786#define mmCP_IQ_WAIT_TIME2 0x10b0 2787#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 2788#define mmCP_RB0_BASE_HI 0x10b1 2789#define mmCP_RB0_BASE_HI_BASE_IDX 0 2790#define mmCP_RB1_BASE_HI 0x10b2 2791#define mmCP_RB1_BASE_HI_BASE_IDX 0 2792#define mmCP_VMID_RESET 0x10b3 2793#define mmCP_VMID_RESET_BASE_IDX 0 2794#define mmCPC_INT_CNTL 0x10b4 2795#define mmCPC_INT_CNTL_BASE_IDX 0 2796#define mmCPC_INT_STATUS 0x10b5 2797#define mmCPC_INT_STATUS_BASE_IDX 0 2798#define mmCP_VMID_PREEMPT 0x10b6 2799#define mmCP_VMID_PREEMPT_BASE_IDX 0 2800#define mmCPC_INT_CNTX_ID 0x10b7 2801#define mmCPC_INT_CNTX_ID_BASE_IDX 0 2802#define mmCP_PQ_STATUS 0x10b8 2803#define mmCP_PQ_STATUS_BASE_IDX 0 2804#define mmCP_CPC_IC_BASE_LO 0x10b9 2805#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0 2806#define mmCP_CPC_IC_BASE_HI 0x10ba 2807#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0 2808#define mmCP_CPC_IC_BASE_CNTL 0x10bb 2809#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0 2810#define mmCP_CPC_IC_OP_CNTL 0x10bc 2811#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0 2812#define mmCP_MEC1_F32_INT_DIS 0x10bd 2813#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 2814#define mmCP_MEC2_F32_INT_DIS 0x10be 2815#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 2816#define mmCP_VMID_STATUS 0x10bf 2817#define mmCP_VMID_STATUS_BASE_IDX 0 2818 2819 2820// addressBlock: gc_cppdec2 2821// base address: 0xc600 2822#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 2823#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 2824#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 2825#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 2826#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 2827#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 2828#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 2829#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 2830#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 2831#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 2832#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 2833#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 2834#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 2835#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 2836#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 2837#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 2838#define mmCP_RB_DOORBELL_CLEAR 0x1188 2839#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 2840#define mmCP_GFX_MQD_CONTROL 0x11a0 2841#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 2842#define mmCP_GFX_MQD_BASE_ADDR 0x11a1 2843#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 2844#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2 2845#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 2846#define mmCP_RB_STATUS 0x11a3 2847#define mmCP_RB_STATUS_BASE_IDX 0 2848#define mmCPG_UTCL1_STATUS 0x11b4 2849#define mmCPG_UTCL1_STATUS_BASE_IDX 0 2850#define mmCPC_UTCL1_STATUS 0x11b5 2851#define mmCPC_UTCL1_STATUS_BASE_IDX 0 2852#define mmCPF_UTCL1_STATUS 0x11b6 2853#define mmCPF_UTCL1_STATUS_BASE_IDX 0 2854#define mmCP_SD_CNTL 0x11b7 2855#define mmCP_SD_CNTL_BASE_IDX 0 2856#define mmCP_SOFT_RESET_CNTL 0x11b9 2857#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 2858#define mmCP_CPC_GFX_CNTL 0x11ba 2859#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 2860 2861 2862// addressBlock: gc_spipdec 2863// base address: 0xc700 2864#define mmSPI_ARB_PRIORITY 0x11c0 2865#define mmSPI_ARB_PRIORITY_BASE_IDX 0 2866#define mmSPI_ARB_CYCLES_0 0x11c1 2867#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 2868#define mmSPI_ARB_CYCLES_1 0x11c2 2869#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 2870#define mmSPI_CDBG_SYS_GFX 0x11c3 2871#define mmSPI_CDBG_SYS_GFX_BASE_IDX 0 2872#define mmSPI_CDBG_SYS_HP3D 0x11c4 2873#define mmSPI_CDBG_SYS_HP3D_BASE_IDX 0 2874#define mmSPI_CDBG_SYS_CS0 0x11c5 2875#define mmSPI_CDBG_SYS_CS0_BASE_IDX 0 2876#define mmSPI_CDBG_SYS_CS1 0x11c6 2877#define mmSPI_CDBG_SYS_CS1_BASE_IDX 0 2878#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7 2879#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 2880#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 2881#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 2882#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9 2883#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 2884#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca 2885#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 2886#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb 2887#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 2888#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc 2889#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 2890#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd 2891#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 2892#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce 2893#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 2894#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf 2895#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 2896#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0 2897#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 2898#define mmSPI_GDBG_WAVE_CNTL 0x11d1 2899#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 2900#define mmSPI_GDBG_TRAP_CONFIG 0x11d2 2901#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 2902#define mmSPI_GDBG_TRAP_MASK 0x11d3 2903#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 2904#define mmSPI_GDBG_WAVE_CNTL2 0x11d4 2905#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 2906#define mmSPI_GDBG_WAVE_CNTL3 0x11d5 2907#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 2908#define mmSPI_GDBG_TRAP_DATA0 0x11d8 2909#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 2910#define mmSPI_GDBG_TRAP_DATA1 0x11d9 2911#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 2912#define mmSPI_COMPUTE_QUEUE_RESET 0x11db 2913#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 2914#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc 2915#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 2916#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd 2917#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 2918#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de 2919#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 2920#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df 2921#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 2922#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0 2923#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 2924#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1 2925#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 2926#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2 2927#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 2928#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3 2929#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 2930#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4 2931#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 2932#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5 2933#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 2934#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 2935#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 2936#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 2937#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 2938#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 2939#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 2940#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 2941#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 2942#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea 2943#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 2944#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb 2945#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 2946#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec 2947#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 2948#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed 2949#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 2950#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee 2951#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 2952#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef 2953#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 2954#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0 2955#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 2956#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1 2957#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 2958#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 2959#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 2960#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 2961#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 2962#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4 2963#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 2964#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5 2965#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 2966#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6 2967#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 2968#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7 2969#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 2970#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 2971#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 2972#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 2973#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 2974#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa 2975#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 2976#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb 2977#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 2978#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc 2979#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 2980#define mmSPI_ARB_CNTL_0 0x11fd 2981#define mmSPI_ARB_CNTL_0_BASE_IDX 0 2982 2983 2984// addressBlock: gc_cpphqddec 2985// base address: 0xc800 2986#define mmCP_HQD_GFX_CONTROL 0x123e 2987#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 2988#define mmCP_HQD_GFX_STATUS 0x123f 2989#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 2990#define mmCP_HPD_ROQ_OFFSETS 0x1240 2991#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 2992#define mmCP_HPD_STATUS0 0x1241 2993#define mmCP_HPD_STATUS0_BASE_IDX 0 2994#define mmCP_HPD_UTCL1_CNTL 0x1242 2995#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 2996#define mmCP_HPD_UTCL1_ERROR 0x1243 2997#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 2998#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244 2999#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 3000#define mmCP_MQD_BASE_ADDR 0x1245 3001#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 3002#define mmCP_MQD_BASE_ADDR_HI 0x1246 3003#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 3004#define mmCP_HQD_ACTIVE 0x1247 3005#define mmCP_HQD_ACTIVE_BASE_IDX 0 3006#define mmCP_HQD_VMID 0x1248 3007#define mmCP_HQD_VMID_BASE_IDX 0 3008#define mmCP_HQD_PERSISTENT_STATE 0x1249 3009#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 3010#define mmCP_HQD_PIPE_PRIORITY 0x124a 3011#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 3012#define mmCP_HQD_QUEUE_PRIORITY 0x124b 3013#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 3014#define mmCP_HQD_QUANTUM 0x124c 3015#define mmCP_HQD_QUANTUM_BASE_IDX 0 3016#define mmCP_HQD_PQ_BASE 0x124d 3017#define mmCP_HQD_PQ_BASE_BASE_IDX 0 3018#define mmCP_HQD_PQ_BASE_HI 0x124e 3019#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 3020#define mmCP_HQD_PQ_RPTR 0x124f 3021#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 3022#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 3023#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 3024#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 3025#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 3026#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 3027#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 3028#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 3029#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 3030#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 3031#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 3032#define mmCP_HQD_PQ_CONTROL 0x1256 3033#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 3034#define mmCP_HQD_IB_BASE_ADDR 0x1257 3035#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 3036#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258 3037#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 3038#define mmCP_HQD_IB_RPTR 0x1259 3039#define mmCP_HQD_IB_RPTR_BASE_IDX 0 3040#define mmCP_HQD_IB_CONTROL 0x125a 3041#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 3042#define mmCP_HQD_IQ_TIMER 0x125b 3043#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 3044#define mmCP_HQD_IQ_RPTR 0x125c 3045#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 3046#define mmCP_HQD_DEQUEUE_REQUEST 0x125d 3047#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 3048#define mmCP_HQD_DMA_OFFLOAD 0x125e 3049#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 3050#define mmCP_HQD_OFFLOAD 0x125e 3051#define mmCP_HQD_OFFLOAD_BASE_IDX 0 3052#define mmCP_HQD_SEMA_CMD 0x125f 3053#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 3054#define mmCP_HQD_MSG_TYPE 0x1260 3055#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 3056#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261 3057#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 3058#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262 3059#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 3060#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263 3061#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 3062#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264 3063#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 3064#define mmCP_HQD_HQ_SCHEDULER0 0x1265 3065#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 3066#define mmCP_HQD_HQ_STATUS0 0x1265 3067#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 3068#define mmCP_HQD_HQ_CONTROL0 0x1266 3069#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 3070#define mmCP_HQD_HQ_SCHEDULER1 0x1266 3071#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 3072#define mmCP_MQD_CONTROL 0x1267 3073#define mmCP_MQD_CONTROL_BASE_IDX 0 3074#define mmCP_HQD_HQ_STATUS1 0x1268 3075#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 3076#define mmCP_HQD_HQ_CONTROL1 0x1269 3077#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 3078#define mmCP_HQD_EOP_BASE_ADDR 0x126a 3079#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 3080#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b 3081#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 3082#define mmCP_HQD_EOP_CONTROL 0x126c 3083#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 3084#define mmCP_HQD_EOP_RPTR 0x126d 3085#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 3086#define mmCP_HQD_EOP_WPTR 0x126e 3087#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 3088#define mmCP_HQD_EOP_EVENTS 0x126f 3089#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 3090#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 3091#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 3092#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 3093#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 3094#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272 3095#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 3096#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273 3097#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 3098#define mmCP_HQD_CNTL_STACK_SIZE 0x1274 3099#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 3100#define mmCP_HQD_WG_STATE_OFFSET 0x1275 3101#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 3102#define mmCP_HQD_CTX_SAVE_SIZE 0x1276 3103#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 3104#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277 3105#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 3106#define mmCP_HQD_ERROR 0x1278 3107#define mmCP_HQD_ERROR_BASE_IDX 0 3108#define mmCP_HQD_EOP_WPTR_MEM 0x1279 3109#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 3110#define mmCP_HQD_AQL_CONTROL 0x127a 3111#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 3112#define mmCP_HQD_PQ_WPTR_LO 0x127b 3113#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 3114#define mmCP_HQD_PQ_WPTR_HI 0x127c 3115#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 3116 3117 3118// addressBlock: gc_didtdec 3119// base address: 0xca00 3120#define mmDIDT_IND_INDEX 0x1280 3121#define mmDIDT_IND_INDEX_BASE_IDX 0 3122#define mmDIDT_IND_DATA 0x1281 3123#define mmDIDT_IND_DATA_BASE_IDX 0 3124#define mmDIDT_INDEX_AUTO_INCR_EN 0x1282 3125#define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 3126 3127 3128// addressBlock: gc_gccacdec 3129// base address: 0xca10 3130#define mmGC_CAC_CTRL_1 0x1284 3131#define mmGC_CAC_CTRL_1_BASE_IDX 0 3132#define mmGC_CAC_CTRL_2 0x1285 3133#define mmGC_CAC_CTRL_2_BASE_IDX 0 3134#define mmGC_CAC_INDEX_AUTO_INCR_EN 0x1286 3135#define mmGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0 3136#define mmGC_CAC_AGGR_LOWER 0x1287 3137#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 3138#define mmGC_CAC_AGGR_UPPER 0x1288 3139#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 3140#define mmPCC_PERF_COUNTER 0x128a 3141#define mmPCC_PERF_COUNTER_BASE_IDX 0 3142#define mmGC_CAC_SOFT_CTRL 0x128d 3143#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 3144#define mmGC_DIDT_CTRL0 0x128e 3145#define mmGC_DIDT_CTRL0_BASE_IDX 0 3146#define mmGC_DIDT_CTRL1 0x128f 3147#define mmGC_DIDT_CTRL1_BASE_IDX 0 3148#define mmGC_DIDT_CTRL2 0x1290 3149#define mmGC_DIDT_CTRL2_BASE_IDX 0 3150#define mmGC_DIDT_WEIGHT 0x1291 3151#define mmGC_DIDT_WEIGHT_BASE_IDX 0 3152#define mmGC_EDC_CTRL 0x1293 3153#define mmGC_EDC_CTRL_BASE_IDX 0 3154#define mmGC_EDC_THRESHOLD 0x1294 3155#define mmGC_EDC_THRESHOLD_BASE_IDX 0 3156#define mmGC_DIDT_DROOP_CTRL 0x1298 3157#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0 3158#define mmGC_DIDT_DROOP_CTRL1 0x1299 3159#define mmGC_DIDT_DROOP_CTRL1_BASE_IDX 0 3160#define mmGC_EDC_DROOP_CTRL 0x129a 3161#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0 3162#define mmGC_THROTTLE_CTRL 0x129b 3163#define mmGC_THROTTLE_CTRL_BASE_IDX 0 3164#define mmGC_CAC_IND_INDEX 0x129c 3165#define mmGC_CAC_IND_INDEX_BASE_IDX 0 3166#define mmGC_CAC_IND_DATA 0x129d 3167#define mmGC_CAC_IND_DATA_BASE_IDX 0 3168#define mmSE_CAC_IND_INDEX 0x129e 3169#define mmSE_CAC_IND_INDEX_BASE_IDX 0 3170#define mmSE_CAC_IND_DATA 0x129f 3171#define mmSE_CAC_IND_DATA_BASE_IDX 0 3172 3173 3174// addressBlock: gc_tcpdec 3175// base address: 0xca80 3176#define mmTCP_WATCH0_ADDR_H 0x12a0 3177#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 3178#define mmTCP_WATCH0_ADDR_L 0x12a1 3179#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 3180#define mmTCP_WATCH0_CNTL 0x12a2 3181#define mmTCP_WATCH0_CNTL_BASE_IDX 0 3182#define mmTCP_WATCH1_ADDR_H 0x12a3 3183#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 3184#define mmTCP_WATCH1_ADDR_L 0x12a4 3185#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 3186#define mmTCP_WATCH1_CNTL 0x12a5 3187#define mmTCP_WATCH1_CNTL_BASE_IDX 0 3188#define mmTCP_WATCH2_ADDR_H 0x12a6 3189#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 3190#define mmTCP_WATCH2_ADDR_L 0x12a7 3191#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 3192#define mmTCP_WATCH2_CNTL 0x12a8 3193#define mmTCP_WATCH2_CNTL_BASE_IDX 0 3194#define mmTCP_WATCH3_ADDR_H 0x12a9 3195#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 3196#define mmTCP_WATCH3_ADDR_L 0x12aa 3197#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 3198#define mmTCP_WATCH3_CNTL 0x12ab 3199#define mmTCP_WATCH3_CNTL_BASE_IDX 0 3200#define mmTCP_GATCL1_CNTL 0x12b0 3201#define mmTCP_GATCL1_CNTL_BASE_IDX 0 3202#define mmTCP_GATCL1_DSM_CNTL 0x12b2 3203#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0 3204#define mmTCP_CNTL2 0x12b4 3205#define mmTCP_CNTL2_BASE_IDX 0 3206#define mmTCP_UTCL1_CNTL1 0x12b5 3207#define mmTCP_UTCL1_CNTL1_BASE_IDX 0 3208#define mmTCP_UTCL1_CNTL2 0x12b6 3209#define mmTCP_UTCL1_CNTL2_BASE_IDX 0 3210#define mmTCP_UTCL1_STATUS 0x12b7 3211#define mmTCP_UTCL1_STATUS_BASE_IDX 0 3212#define mmTCP_PERFCOUNTER_FILTER 0x12b9 3213#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 3214#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba 3215#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 3216 3217 3218// addressBlock: gc_gdspdec 3219// base address: 0xcc00 3220#define mmGDS_VMID0_BASE 0x1300 3221#define mmGDS_VMID0_BASE_BASE_IDX 0 3222#define mmGDS_VMID0_SIZE 0x1301 3223#define mmGDS_VMID0_SIZE_BASE_IDX 0 3224#define mmGDS_VMID1_BASE 0x1302 3225#define mmGDS_VMID1_BASE_BASE_IDX 0 3226#define mmGDS_VMID1_SIZE 0x1303 3227#define mmGDS_VMID1_SIZE_BASE_IDX 0 3228#define mmGDS_VMID2_BASE 0x1304 3229#define mmGDS_VMID2_BASE_BASE_IDX 0 3230#define mmGDS_VMID2_SIZE 0x1305 3231#define mmGDS_VMID2_SIZE_BASE_IDX 0 3232#define mmGDS_VMID3_BASE 0x1306 3233#define mmGDS_VMID3_BASE_BASE_IDX 0 3234#define mmGDS_VMID3_SIZE 0x1307 3235#define mmGDS_VMID3_SIZE_BASE_IDX 0 3236#define mmGDS_VMID4_BASE 0x1308 3237#define mmGDS_VMID4_BASE_BASE_IDX 0 3238#define mmGDS_VMID4_SIZE 0x1309 3239#define mmGDS_VMID4_SIZE_BASE_IDX 0 3240#define mmGDS_VMID5_BASE 0x130a 3241#define mmGDS_VMID5_BASE_BASE_IDX 0 3242#define mmGDS_VMID5_SIZE 0x130b 3243#define mmGDS_VMID5_SIZE_BASE_IDX 0 3244#define mmGDS_VMID6_BASE 0x130c 3245#define mmGDS_VMID6_BASE_BASE_IDX 0 3246#define mmGDS_VMID6_SIZE 0x130d 3247#define mmGDS_VMID6_SIZE_BASE_IDX 0 3248#define mmGDS_VMID7_BASE 0x130e 3249#define mmGDS_VMID7_BASE_BASE_IDX 0 3250#define mmGDS_VMID7_SIZE 0x130f 3251#define mmGDS_VMID7_SIZE_BASE_IDX 0 3252#define mmGDS_VMID8_BASE 0x1310 3253#define mmGDS_VMID8_BASE_BASE_IDX 0 3254#define mmGDS_VMID8_SIZE 0x1311 3255#define mmGDS_VMID8_SIZE_BASE_IDX 0 3256#define mmGDS_VMID9_BASE 0x1312 3257#define mmGDS_VMID9_BASE_BASE_IDX 0 3258#define mmGDS_VMID9_SIZE 0x1313 3259#define mmGDS_VMID9_SIZE_BASE_IDX 0 3260#define mmGDS_VMID10_BASE 0x1314 3261#define mmGDS_VMID10_BASE_BASE_IDX 0 3262#define mmGDS_VMID10_SIZE 0x1315 3263#define mmGDS_VMID10_SIZE_BASE_IDX 0 3264#define mmGDS_VMID11_BASE 0x1316 3265#define mmGDS_VMID11_BASE_BASE_IDX 0 3266#define mmGDS_VMID11_SIZE 0x1317 3267#define mmGDS_VMID11_SIZE_BASE_IDX 0 3268#define mmGDS_VMID12_BASE 0x1318 3269#define mmGDS_VMID12_BASE_BASE_IDX 0 3270#define mmGDS_VMID12_SIZE 0x1319 3271#define mmGDS_VMID12_SIZE_BASE_IDX 0 3272#define mmGDS_VMID13_BASE 0x131a 3273#define mmGDS_VMID13_BASE_BASE_IDX 0 3274#define mmGDS_VMID13_SIZE 0x131b 3275#define mmGDS_VMID13_SIZE_BASE_IDX 0 3276#define mmGDS_VMID14_BASE 0x131c 3277#define mmGDS_VMID14_BASE_BASE_IDX 0 3278#define mmGDS_VMID14_SIZE 0x131d 3279#define mmGDS_VMID14_SIZE_BASE_IDX 0 3280#define mmGDS_VMID15_BASE 0x131e 3281#define mmGDS_VMID15_BASE_BASE_IDX 0 3282#define mmGDS_VMID15_SIZE 0x131f 3283#define mmGDS_VMID15_SIZE_BASE_IDX 0 3284#define mmGDS_GWS_VMID0 0x1320 3285#define mmGDS_GWS_VMID0_BASE_IDX 0 3286#define mmGDS_GWS_VMID1 0x1321 3287#define mmGDS_GWS_VMID1_BASE_IDX 0 3288#define mmGDS_GWS_VMID2 0x1322 3289#define mmGDS_GWS_VMID2_BASE_IDX 0 3290#define mmGDS_GWS_VMID3 0x1323 3291#define mmGDS_GWS_VMID3_BASE_IDX 0 3292#define mmGDS_GWS_VMID4 0x1324 3293#define mmGDS_GWS_VMID4_BASE_IDX 0 3294#define mmGDS_GWS_VMID5 0x1325 3295#define mmGDS_GWS_VMID5_BASE_IDX 0 3296#define mmGDS_GWS_VMID6 0x1326 3297#define mmGDS_GWS_VMID6_BASE_IDX 0 3298#define mmGDS_GWS_VMID7 0x1327 3299#define mmGDS_GWS_VMID7_BASE_IDX 0 3300#define mmGDS_GWS_VMID8 0x1328 3301#define mmGDS_GWS_VMID8_BASE_IDX 0 3302#define mmGDS_GWS_VMID9 0x1329 3303#define mmGDS_GWS_VMID9_BASE_IDX 0 3304#define mmGDS_GWS_VMID10 0x132a 3305#define mmGDS_GWS_VMID10_BASE_IDX 0 3306#define mmGDS_GWS_VMID11 0x132b 3307#define mmGDS_GWS_VMID11_BASE_IDX 0 3308#define mmGDS_GWS_VMID12 0x132c 3309#define mmGDS_GWS_VMID12_BASE_IDX 0 3310#define mmGDS_GWS_VMID13 0x132d 3311#define mmGDS_GWS_VMID13_BASE_IDX 0 3312#define mmGDS_GWS_VMID14 0x132e 3313#define mmGDS_GWS_VMID14_BASE_IDX 0 3314#define mmGDS_GWS_VMID15 0x132f 3315#define mmGDS_GWS_VMID15_BASE_IDX 0 3316#define mmGDS_OA_VMID0 0x1330 3317#define mmGDS_OA_VMID0_BASE_IDX 0 3318#define mmGDS_OA_VMID1 0x1331 3319#define mmGDS_OA_VMID1_BASE_IDX 0 3320#define mmGDS_OA_VMID2 0x1332 3321#define mmGDS_OA_VMID2_BASE_IDX 0 3322#define mmGDS_OA_VMID3 0x1333 3323#define mmGDS_OA_VMID3_BASE_IDX 0 3324#define mmGDS_OA_VMID4 0x1334 3325#define mmGDS_OA_VMID4_BASE_IDX 0 3326#define mmGDS_OA_VMID5 0x1335 3327#define mmGDS_OA_VMID5_BASE_IDX 0 3328#define mmGDS_OA_VMID6 0x1336 3329#define mmGDS_OA_VMID6_BASE_IDX 0 3330#define mmGDS_OA_VMID7 0x1337 3331#define mmGDS_OA_VMID7_BASE_IDX 0 3332#define mmGDS_OA_VMID8 0x1338 3333#define mmGDS_OA_VMID8_BASE_IDX 0 3334#define mmGDS_OA_VMID9 0x1339 3335#define mmGDS_OA_VMID9_BASE_IDX 0 3336#define mmGDS_OA_VMID10 0x133a 3337#define mmGDS_OA_VMID10_BASE_IDX 0 3338#define mmGDS_OA_VMID11 0x133b 3339#define mmGDS_OA_VMID11_BASE_IDX 0 3340#define mmGDS_OA_VMID12 0x133c 3341#define mmGDS_OA_VMID12_BASE_IDX 0 3342#define mmGDS_OA_VMID13 0x133d 3343#define mmGDS_OA_VMID13_BASE_IDX 0 3344#define mmGDS_OA_VMID14 0x133e 3345#define mmGDS_OA_VMID14_BASE_IDX 0 3346#define mmGDS_OA_VMID15 0x133f 3347#define mmGDS_OA_VMID15_BASE_IDX 0 3348#define mmGDS_GWS_RESET0 0x1344 3349#define mmGDS_GWS_RESET0_BASE_IDX 0 3350#define mmGDS_GWS_RESET1 0x1345 3351#define mmGDS_GWS_RESET1_BASE_IDX 0 3352#define mmGDS_GWS_RESOURCE_RESET 0x1346 3353#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 3354#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348 3355#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 3356#define mmGDS_OA_RESET_MASK 0x1349 3357#define mmGDS_OA_RESET_MASK_BASE_IDX 0 3358#define mmGDS_OA_RESET 0x134a 3359#define mmGDS_OA_RESET_BASE_IDX 0 3360#define mmGDS_ENHANCE 0x134b 3361#define mmGDS_ENHANCE_BASE_IDX 0 3362#define mmGDS_OA_CGPG_RESTORE 0x134c 3363#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 3364#define mmGDS_CS_CTXSW_STATUS 0x134d 3365#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 3366#define mmGDS_CS_CTXSW_CNT0 0x134e 3367#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 3368#define mmGDS_CS_CTXSW_CNT1 0x134f 3369#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 3370#define mmGDS_CS_CTXSW_CNT2 0x1350 3371#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 3372#define mmGDS_CS_CTXSW_CNT3 0x1351 3373#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 3374#define mmGDS_GFX_CTXSW_STATUS 0x1352 3375#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 3376#define mmGDS_VS_CTXSW_CNT0 0x1353 3377#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 3378#define mmGDS_VS_CTXSW_CNT1 0x1354 3379#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 3380#define mmGDS_VS_CTXSW_CNT2 0x1355 3381#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 3382#define mmGDS_VS_CTXSW_CNT3 0x1356 3383#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 3384#define mmGDS_PS0_CTXSW_CNT0 0x1357 3385#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0 3386#define mmGDS_PS0_CTXSW_CNT1 0x1358 3387#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0 3388#define mmGDS_PS0_CTXSW_CNT2 0x1359 3389#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0 3390#define mmGDS_PS0_CTXSW_CNT3 0x135a 3391#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0 3392#define mmGDS_PS1_CTXSW_CNT0 0x135b 3393#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0 3394#define mmGDS_PS1_CTXSW_CNT1 0x135c 3395#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0 3396#define mmGDS_PS1_CTXSW_CNT2 0x135d 3397#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0 3398#define mmGDS_PS1_CTXSW_CNT3 0x135e 3399#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0 3400#define mmGDS_PS2_CTXSW_CNT0 0x135f 3401#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0 3402#define mmGDS_PS2_CTXSW_CNT1 0x1360 3403#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0 3404#define mmGDS_PS2_CTXSW_CNT2 0x1361 3405#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0 3406#define mmGDS_PS2_CTXSW_CNT3 0x1362 3407#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0 3408#define mmGDS_PS3_CTXSW_CNT0 0x1363 3409#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0 3410#define mmGDS_PS3_CTXSW_CNT1 0x1364 3411#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0 3412#define mmGDS_PS3_CTXSW_CNT2 0x1365 3413#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0 3414#define mmGDS_PS3_CTXSW_CNT3 0x1366 3415#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0 3416#define mmGDS_PS4_CTXSW_CNT0 0x1367 3417#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0 3418#define mmGDS_PS4_CTXSW_CNT1 0x1368 3419#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0 3420#define mmGDS_PS4_CTXSW_CNT2 0x1369 3421#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0 3422#define mmGDS_PS4_CTXSW_CNT3 0x136a 3423#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0 3424#define mmGDS_PS5_CTXSW_CNT0 0x136b 3425#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0 3426#define mmGDS_PS5_CTXSW_CNT1 0x136c 3427#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0 3428#define mmGDS_PS5_CTXSW_CNT2 0x136d 3429#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0 3430#define mmGDS_PS5_CTXSW_CNT3 0x136e 3431#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0 3432#define mmGDS_PS6_CTXSW_CNT0 0x136f 3433#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0 3434#define mmGDS_PS6_CTXSW_CNT1 0x1370 3435#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0 3436#define mmGDS_PS6_CTXSW_CNT2 0x1371 3437#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0 3438#define mmGDS_PS6_CTXSW_CNT3 0x1372 3439#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0 3440#define mmGDS_PS7_CTXSW_CNT0 0x1373 3441#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0 3442#define mmGDS_PS7_CTXSW_CNT1 0x1374 3443#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0 3444#define mmGDS_PS7_CTXSW_CNT2 0x1375 3445#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0 3446#define mmGDS_PS7_CTXSW_CNT3 0x1376 3447#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0 3448#define mmGDS_GS_CTXSW_CNT0 0x1377 3449#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 3450#define mmGDS_GS_CTXSW_CNT1 0x1378 3451#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 3452#define mmGDS_GS_CTXSW_CNT2 0x1379 3453#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 3454#define mmGDS_GS_CTXSW_CNT3 0x137a 3455#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 3456 3457 3458// addressBlock: gc_rasdec 3459// base address: 0xce00 3460#define mmRAS_SIGNATURE_CONTROL 0x1380 3461#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0 3462#define mmRAS_SIGNATURE_MASK 0x1381 3463#define mmRAS_SIGNATURE_MASK_BASE_IDX 0 3464#define mmRAS_SX_SIGNATURE0 0x1382 3465#define mmRAS_SX_SIGNATURE0_BASE_IDX 0 3466#define mmRAS_SX_SIGNATURE1 0x1383 3467#define mmRAS_SX_SIGNATURE1_BASE_IDX 0 3468#define mmRAS_SX_SIGNATURE2 0x1384 3469#define mmRAS_SX_SIGNATURE2_BASE_IDX 0 3470#define mmRAS_SX_SIGNATURE3 0x1385 3471#define mmRAS_SX_SIGNATURE3_BASE_IDX 0 3472#define mmRAS_DB_SIGNATURE0 0x138b 3473#define mmRAS_DB_SIGNATURE0_BASE_IDX 0 3474#define mmRAS_PA_SIGNATURE0 0x138c 3475#define mmRAS_PA_SIGNATURE0_BASE_IDX 0 3476#define mmRAS_VGT_SIGNATURE0 0x138d 3477#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0 3478#define mmRAS_SQ_SIGNATURE0 0x138e 3479#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0 3480#define mmRAS_SC_SIGNATURE0 0x138f 3481#define mmRAS_SC_SIGNATURE0_BASE_IDX 0 3482#define mmRAS_SC_SIGNATURE1 0x1390 3483#define mmRAS_SC_SIGNATURE1_BASE_IDX 0 3484#define mmRAS_SC_SIGNATURE2 0x1391 3485#define mmRAS_SC_SIGNATURE2_BASE_IDX 0 3486#define mmRAS_SC_SIGNATURE3 0x1392 3487#define mmRAS_SC_SIGNATURE3_BASE_IDX 0 3488#define mmRAS_SC_SIGNATURE4 0x1393 3489#define mmRAS_SC_SIGNATURE4_BASE_IDX 0 3490#define mmRAS_SC_SIGNATURE5 0x1394 3491#define mmRAS_SC_SIGNATURE5_BASE_IDX 0 3492#define mmRAS_SC_SIGNATURE6 0x1395 3493#define mmRAS_SC_SIGNATURE6_BASE_IDX 0 3494#define mmRAS_SC_SIGNATURE7 0x1396 3495#define mmRAS_SC_SIGNATURE7_BASE_IDX 0 3496#define mmRAS_IA_SIGNATURE0 0x1397 3497#define mmRAS_IA_SIGNATURE0_BASE_IDX 0 3498#define mmRAS_IA_SIGNATURE1 0x1398 3499#define mmRAS_IA_SIGNATURE1_BASE_IDX 0 3500#define mmRAS_SPI_SIGNATURE0 0x1399 3501#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0 3502#define mmRAS_SPI_SIGNATURE1 0x139a 3503#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0 3504#define mmRAS_TA_SIGNATURE0 0x139b 3505#define mmRAS_TA_SIGNATURE0_BASE_IDX 0 3506#define mmRAS_TD_SIGNATURE0 0x139c 3507#define mmRAS_TD_SIGNATURE0_BASE_IDX 0 3508#define mmRAS_CB_SIGNATURE0 0x139d 3509#define mmRAS_CB_SIGNATURE0_BASE_IDX 0 3510#define mmRAS_BCI_SIGNATURE0 0x139e 3511#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0 3512#define mmRAS_BCI_SIGNATURE1 0x139f 3513#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0 3514#define mmRAS_TA_SIGNATURE1 0x13a0 3515#define mmRAS_TA_SIGNATURE1_BASE_IDX 0 3516 3517 3518// addressBlock: gc_gfxdec0 3519// base address: 0x28000 3520#define mmDB_RENDER_CONTROL 0x0000 3521#define mmDB_RENDER_CONTROL_BASE_IDX 1 3522#define mmDB_COUNT_CONTROL 0x0001 3523#define mmDB_COUNT_CONTROL_BASE_IDX 1 3524#define mmDB_DEPTH_VIEW 0x0002 3525#define mmDB_DEPTH_VIEW_BASE_IDX 1 3526#define mmDB_RENDER_OVERRIDE 0x0003 3527#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 3528#define mmDB_RENDER_OVERRIDE2 0x0004 3529#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 3530#define mmDB_HTILE_DATA_BASE 0x0005 3531#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 3532#define mmDB_HTILE_DATA_BASE_HI 0x0006 3533#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 3534#define mmDB_DEPTH_SIZE 0x0007 3535#define mmDB_DEPTH_SIZE_BASE_IDX 1 3536#define mmDB_DEPTH_BOUNDS_MIN 0x0008 3537#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 3538#define mmDB_DEPTH_BOUNDS_MAX 0x0009 3539#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 3540#define mmDB_STENCIL_CLEAR 0x000a 3541#define mmDB_STENCIL_CLEAR_BASE_IDX 1 3542#define mmDB_DEPTH_CLEAR 0x000b 3543#define mmDB_DEPTH_CLEAR_BASE_IDX 1 3544#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c 3545#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 3546#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d 3547#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 3548#define mmDB_Z_INFO 0x000e 3549#define mmDB_Z_INFO_BASE_IDX 1 3550#define mmDB_STENCIL_INFO 0x000f 3551#define mmDB_STENCIL_INFO_BASE_IDX 1 3552#define mmDB_Z_READ_BASE 0x0010 3553#define mmDB_Z_READ_BASE_BASE_IDX 1 3554#define mmDB_Z_READ_BASE_HI 0x0011 3555#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 3556#define mmDB_STENCIL_READ_BASE 0x0012 3557#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 3558#define mmDB_STENCIL_READ_BASE_HI 0x0013 3559#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 3560#define mmDB_Z_WRITE_BASE 0x0014 3561#define mmDB_Z_WRITE_BASE_BASE_IDX 1 3562#define mmDB_Z_WRITE_BASE_HI 0x0015 3563#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 3564#define mmDB_STENCIL_WRITE_BASE 0x0016 3565#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 3566#define mmDB_STENCIL_WRITE_BASE_HI 0x0017 3567#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3568#define mmDB_DFSM_CONTROL 0x0018 3569#define mmDB_DFSM_CONTROL_BASE_IDX 1 3570#define mmDB_Z_INFO2 0x001a 3571#define mmDB_Z_INFO2_BASE_IDX 1 3572#define mmDB_STENCIL_INFO2 0x001b 3573#define mmDB_STENCIL_INFO2_BASE_IDX 1 3574#define mmTA_BC_BASE_ADDR 0x0020 3575#define mmTA_BC_BASE_ADDR_BASE_IDX 1 3576#define mmTA_BC_BASE_ADDR_HI 0x0021 3577#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 3578#define mmCOHER_DEST_BASE_HI_0 0x007a 3579#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 3580#define mmCOHER_DEST_BASE_HI_1 0x007b 3581#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 3582#define mmCOHER_DEST_BASE_HI_2 0x007c 3583#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 3584#define mmCOHER_DEST_BASE_HI_3 0x007d 3585#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 3586#define mmCOHER_DEST_BASE_2 0x007e 3587#define mmCOHER_DEST_BASE_2_BASE_IDX 1 3588#define mmCOHER_DEST_BASE_3 0x007f 3589#define mmCOHER_DEST_BASE_3_BASE_IDX 1 3590#define mmPA_SC_WINDOW_OFFSET 0x0080 3591#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 3592#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 3593#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 3594#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 3595#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 3596#define mmPA_SC_CLIPRECT_RULE 0x0083 3597#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 3598#define mmPA_SC_CLIPRECT_0_TL 0x0084 3599#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 3600#define mmPA_SC_CLIPRECT_0_BR 0x0085 3601#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 3602#define mmPA_SC_CLIPRECT_1_TL 0x0086 3603#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 3604#define mmPA_SC_CLIPRECT_1_BR 0x0087 3605#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 3606#define mmPA_SC_CLIPRECT_2_TL 0x0088 3607#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 3608#define mmPA_SC_CLIPRECT_2_BR 0x0089 3609#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 3610#define mmPA_SC_CLIPRECT_3_TL 0x008a 3611#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 3612#define mmPA_SC_CLIPRECT_3_BR 0x008b 3613#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 3614#define mmPA_SC_EDGERULE 0x008c 3615#define mmPA_SC_EDGERULE_BASE_IDX 1 3616#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 3617#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 3618#define mmCB_TARGET_MASK 0x008e 3619#define mmCB_TARGET_MASK_BASE_IDX 1 3620#define mmCB_SHADER_MASK 0x008f 3621#define mmCB_SHADER_MASK_BASE_IDX 1 3622#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 3623#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 3624#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 3625#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 3626#define mmCOHER_DEST_BASE_0 0x0092 3627#define mmCOHER_DEST_BASE_0_BASE_IDX 1 3628#define mmCOHER_DEST_BASE_1 0x0093 3629#define mmCOHER_DEST_BASE_1_BASE_IDX 1 3630#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 3631#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 3632#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 3633#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 3634#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 3635#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 3636#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 3637#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 3638#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 3639#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 3640#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 3641#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 3642#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a 3643#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 3644#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b 3645#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 3646#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c 3647#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 3648#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d 3649#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 3650#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e 3651#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 3652#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f 3653#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 3654#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 3655#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 3656#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 3657#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 3658#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 3659#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 3660#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 3661#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 3662#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 3663#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 3664#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 3665#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 3666#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 3667#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 3668#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 3669#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 3670#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 3671#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 3672#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 3673#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 3674#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa 3675#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 3676#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab 3677#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 3678#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac 3679#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 3680#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad 3681#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 3682#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae 3683#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 3684#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af 3685#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 3686#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 3687#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 3688#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 3689#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 3690#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 3691#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 3692#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 3693#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 3694#define mmPA_SC_VPORT_ZMIN_0 0x00b4 3695#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 3696#define mmPA_SC_VPORT_ZMAX_0 0x00b5 3697#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 3698#define mmPA_SC_VPORT_ZMIN_1 0x00b6 3699#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 3700#define mmPA_SC_VPORT_ZMAX_1 0x00b7 3701#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 3702#define mmPA_SC_VPORT_ZMIN_2 0x00b8 3703#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 3704#define mmPA_SC_VPORT_ZMAX_2 0x00b9 3705#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 3706#define mmPA_SC_VPORT_ZMIN_3 0x00ba 3707#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 3708#define mmPA_SC_VPORT_ZMAX_3 0x00bb 3709#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 3710#define mmPA_SC_VPORT_ZMIN_4 0x00bc 3711#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 3712#define mmPA_SC_VPORT_ZMAX_4 0x00bd 3713#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 3714#define mmPA_SC_VPORT_ZMIN_5 0x00be 3715#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 3716#define mmPA_SC_VPORT_ZMAX_5 0x00bf 3717#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 3718#define mmPA_SC_VPORT_ZMIN_6 0x00c0 3719#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 3720#define mmPA_SC_VPORT_ZMAX_6 0x00c1 3721#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 3722#define mmPA_SC_VPORT_ZMIN_7 0x00c2 3723#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 3724#define mmPA_SC_VPORT_ZMAX_7 0x00c3 3725#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 3726#define mmPA_SC_VPORT_ZMIN_8 0x00c4 3727#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 3728#define mmPA_SC_VPORT_ZMAX_8 0x00c5 3729#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 3730#define mmPA_SC_VPORT_ZMIN_9 0x00c6 3731#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 3732#define mmPA_SC_VPORT_ZMAX_9 0x00c7 3733#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 3734#define mmPA_SC_VPORT_ZMIN_10 0x00c8 3735#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 3736#define mmPA_SC_VPORT_ZMAX_10 0x00c9 3737#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 3738#define mmPA_SC_VPORT_ZMIN_11 0x00ca 3739#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 3740#define mmPA_SC_VPORT_ZMAX_11 0x00cb 3741#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 3742#define mmPA_SC_VPORT_ZMIN_12 0x00cc 3743#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 3744#define mmPA_SC_VPORT_ZMAX_12 0x00cd 3745#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 3746#define mmPA_SC_VPORT_ZMIN_13 0x00ce 3747#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 3748#define mmPA_SC_VPORT_ZMAX_13 0x00cf 3749#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 3750#define mmPA_SC_VPORT_ZMIN_14 0x00d0 3751#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 3752#define mmPA_SC_VPORT_ZMAX_14 0x00d1 3753#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 3754#define mmPA_SC_VPORT_ZMIN_15 0x00d2 3755#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 3756#define mmPA_SC_VPORT_ZMAX_15 0x00d3 3757#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 3758#define mmPA_SC_RASTER_CONFIG 0x00d4 3759#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 3760#define mmPA_SC_RASTER_CONFIG_1 0x00d5 3761#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 3762#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 3763#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 3764#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 3765#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 3766#define mmCP_PERFMON_CNTX_CNTL 0x00d8 3767#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 3768#define mmCP_PIPEID 0x00d9 3769#define mmCP_PIPEID_BASE_IDX 1 3770#define mmCP_RINGID 0x00d9 3771#define mmCP_RINGID_BASE_IDX 1 3772#define mmCP_VMID 0x00da 3773#define mmCP_VMID_BASE_IDX 1 3774#define mmPA_SC_RIGHT_VERT_GRID 0x00e8 3775#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 3776#define mmPA_SC_LEFT_VERT_GRID 0x00e9 3777#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3778#define mmPA_SC_HORIZ_GRID 0x00ea 3779#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 3780#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3781#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3782#define mmCB_BLEND_RED 0x0105 3783#define mmCB_BLEND_RED_BASE_IDX 1 3784#define mmCB_BLEND_GREEN 0x0106 3785#define mmCB_BLEND_GREEN_BASE_IDX 1 3786#define mmCB_BLEND_BLUE 0x0107 3787#define mmCB_BLEND_BLUE_BASE_IDX 1 3788#define mmCB_BLEND_ALPHA 0x0108 3789#define mmCB_BLEND_ALPHA_BASE_IDX 1 3790#define mmCB_DCC_CONTROL 0x0109 3791#define mmCB_DCC_CONTROL_BASE_IDX 1 3792#define mmDB_STENCIL_CONTROL 0x010b 3793#define mmDB_STENCIL_CONTROL_BASE_IDX 1 3794#define mmDB_STENCILREFMASK 0x010c 3795#define mmDB_STENCILREFMASK_BASE_IDX 1 3796#define mmDB_STENCILREFMASK_BF 0x010d 3797#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 3798#define mmPA_CL_VPORT_XSCALE 0x010f 3799#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 3800#define mmPA_CL_VPORT_XOFFSET 0x0110 3801#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 3802#define mmPA_CL_VPORT_YSCALE 0x0111 3803#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 3804#define mmPA_CL_VPORT_YOFFSET 0x0112 3805#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 3806#define mmPA_CL_VPORT_ZSCALE 0x0113 3807#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 3808#define mmPA_CL_VPORT_ZOFFSET 0x0114 3809#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 3810#define mmPA_CL_VPORT_XSCALE_1 0x0115 3811#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 3812#define mmPA_CL_VPORT_XOFFSET_1 0x0116 3813#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 3814#define mmPA_CL_VPORT_YSCALE_1 0x0117 3815#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 3816#define mmPA_CL_VPORT_YOFFSET_1 0x0118 3817#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 3818#define mmPA_CL_VPORT_ZSCALE_1 0x0119 3819#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 3820#define mmPA_CL_VPORT_ZOFFSET_1 0x011a 3821#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 3822#define mmPA_CL_VPORT_XSCALE_2 0x011b 3823#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 3824#define mmPA_CL_VPORT_XOFFSET_2 0x011c 3825#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 3826#define mmPA_CL_VPORT_YSCALE_2 0x011d 3827#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 3828#define mmPA_CL_VPORT_YOFFSET_2 0x011e 3829#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 3830#define mmPA_CL_VPORT_ZSCALE_2 0x011f 3831#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 3832#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 3833#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 3834#define mmPA_CL_VPORT_XSCALE_3 0x0121 3835#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 3836#define mmPA_CL_VPORT_XOFFSET_3 0x0122 3837#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 3838#define mmPA_CL_VPORT_YSCALE_3 0x0123 3839#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 3840#define mmPA_CL_VPORT_YOFFSET_3 0x0124 3841#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 3842#define mmPA_CL_VPORT_ZSCALE_3 0x0125 3843#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 3844#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 3845#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 3846#define mmPA_CL_VPORT_XSCALE_4 0x0127 3847#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 3848#define mmPA_CL_VPORT_XOFFSET_4 0x0128 3849#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 3850#define mmPA_CL_VPORT_YSCALE_4 0x0129 3851#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 3852#define mmPA_CL_VPORT_YOFFSET_4 0x012a 3853#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 3854#define mmPA_CL_VPORT_ZSCALE_4 0x012b 3855#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 3856#define mmPA_CL_VPORT_ZOFFSET_4 0x012c 3857#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 3858#define mmPA_CL_VPORT_XSCALE_5 0x012d 3859#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 3860#define mmPA_CL_VPORT_XOFFSET_5 0x012e 3861#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 3862#define mmPA_CL_VPORT_YSCALE_5 0x012f 3863#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 3864#define mmPA_CL_VPORT_YOFFSET_5 0x0130 3865#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 3866#define mmPA_CL_VPORT_ZSCALE_5 0x0131 3867#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 3868#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 3869#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 3870#define mmPA_CL_VPORT_XSCALE_6 0x0133 3871#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 3872#define mmPA_CL_VPORT_XOFFSET_6 0x0134 3873#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 3874#define mmPA_CL_VPORT_YSCALE_6 0x0135 3875#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 3876#define mmPA_CL_VPORT_YOFFSET_6 0x0136 3877#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 3878#define mmPA_CL_VPORT_ZSCALE_6 0x0137 3879#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 3880#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 3881#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 3882#define mmPA_CL_VPORT_XSCALE_7 0x0139 3883#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 3884#define mmPA_CL_VPORT_XOFFSET_7 0x013a 3885#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 3886#define mmPA_CL_VPORT_YSCALE_7 0x013b 3887#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 3888#define mmPA_CL_VPORT_YOFFSET_7 0x013c 3889#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 3890#define mmPA_CL_VPORT_ZSCALE_7 0x013d 3891#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 3892#define mmPA_CL_VPORT_ZOFFSET_7 0x013e 3893#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 3894#define mmPA_CL_VPORT_XSCALE_8 0x013f 3895#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 3896#define mmPA_CL_VPORT_XOFFSET_8 0x0140 3897#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 3898#define mmPA_CL_VPORT_YSCALE_8 0x0141 3899#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 3900#define mmPA_CL_VPORT_YOFFSET_8 0x0142 3901#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 3902#define mmPA_CL_VPORT_ZSCALE_8 0x0143 3903#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 3904#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 3905#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 3906#define mmPA_CL_VPORT_XSCALE_9 0x0145 3907#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 3908#define mmPA_CL_VPORT_XOFFSET_9 0x0146 3909#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 3910#define mmPA_CL_VPORT_YSCALE_9 0x0147 3911#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 3912#define mmPA_CL_VPORT_YOFFSET_9 0x0148 3913#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 3914#define mmPA_CL_VPORT_ZSCALE_9 0x0149 3915#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 3916#define mmPA_CL_VPORT_ZOFFSET_9 0x014a 3917#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 3918#define mmPA_CL_VPORT_XSCALE_10 0x014b 3919#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 3920#define mmPA_CL_VPORT_XOFFSET_10 0x014c 3921#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 3922#define mmPA_CL_VPORT_YSCALE_10 0x014d 3923#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 3924#define mmPA_CL_VPORT_YOFFSET_10 0x014e 3925#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 3926#define mmPA_CL_VPORT_ZSCALE_10 0x014f 3927#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 3928#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 3929#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 3930#define mmPA_CL_VPORT_XSCALE_11 0x0151 3931#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 3932#define mmPA_CL_VPORT_XOFFSET_11 0x0152 3933#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 3934#define mmPA_CL_VPORT_YSCALE_11 0x0153 3935#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 3936#define mmPA_CL_VPORT_YOFFSET_11 0x0154 3937#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 3938#define mmPA_CL_VPORT_ZSCALE_11 0x0155 3939#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 3940#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 3941#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 3942#define mmPA_CL_VPORT_XSCALE_12 0x0157 3943#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 3944#define mmPA_CL_VPORT_XOFFSET_12 0x0158 3945#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 3946#define mmPA_CL_VPORT_YSCALE_12 0x0159 3947#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1 3948#define mmPA_CL_VPORT_YOFFSET_12 0x015a 3949#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 3950#define mmPA_CL_VPORT_ZSCALE_12 0x015b 3951#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 3952#define mmPA_CL_VPORT_ZOFFSET_12 0x015c 3953#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 3954#define mmPA_CL_VPORT_XSCALE_13 0x015d 3955#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 3956#define mmPA_CL_VPORT_XOFFSET_13 0x015e 3957#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 3958#define mmPA_CL_VPORT_YSCALE_13 0x015f 3959#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 3960#define mmPA_CL_VPORT_YOFFSET_13 0x0160 3961#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 3962#define mmPA_CL_VPORT_ZSCALE_13 0x0161 3963#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 3964#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 3965#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 3966#define mmPA_CL_VPORT_XSCALE_14 0x0163 3967#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 3968#define mmPA_CL_VPORT_XOFFSET_14 0x0164 3969#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 3970#define mmPA_CL_VPORT_YSCALE_14 0x0165 3971#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 3972#define mmPA_CL_VPORT_YOFFSET_14 0x0166 3973#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 3974#define mmPA_CL_VPORT_ZSCALE_14 0x0167 3975#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 3976#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 3977#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 3978#define mmPA_CL_VPORT_XSCALE_15 0x0169 3979#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 3980#define mmPA_CL_VPORT_XOFFSET_15 0x016a 3981#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 3982#define mmPA_CL_VPORT_YSCALE_15 0x016b 3983#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 3984#define mmPA_CL_VPORT_YOFFSET_15 0x016c 3985#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 3986#define mmPA_CL_VPORT_ZSCALE_15 0x016d 3987#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 3988#define mmPA_CL_VPORT_ZOFFSET_15 0x016e 3989#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 3990#define mmPA_CL_UCP_0_X 0x016f 3991#define mmPA_CL_UCP_0_X_BASE_IDX 1 3992#define mmPA_CL_UCP_0_Y 0x0170 3993#define mmPA_CL_UCP_0_Y_BASE_IDX 1 3994#define mmPA_CL_UCP_0_Z 0x0171 3995#define mmPA_CL_UCP_0_Z_BASE_IDX 1 3996#define mmPA_CL_UCP_0_W 0x0172 3997#define mmPA_CL_UCP_0_W_BASE_IDX 1 3998#define mmPA_CL_UCP_1_X 0x0173 3999#define mmPA_CL_UCP_1_X_BASE_IDX 1 4000#define mmPA_CL_UCP_1_Y 0x0174 4001#define mmPA_CL_UCP_1_Y_BASE_IDX 1 4002#define mmPA_CL_UCP_1_Z 0x0175 4003#define mmPA_CL_UCP_1_Z_BASE_IDX 1 4004#define mmPA_CL_UCP_1_W 0x0176 4005#define mmPA_CL_UCP_1_W_BASE_IDX 1 4006#define mmPA_CL_UCP_2_X 0x0177 4007#define mmPA_CL_UCP_2_X_BASE_IDX 1 4008#define mmPA_CL_UCP_2_Y 0x0178 4009#define mmPA_CL_UCP_2_Y_BASE_IDX 1 4010#define mmPA_CL_UCP_2_Z 0x0179 4011#define mmPA_CL_UCP_2_Z_BASE_IDX 1 4012#define mmPA_CL_UCP_2_W 0x017a 4013#define mmPA_CL_UCP_2_W_BASE_IDX 1 4014#define mmPA_CL_UCP_3_X 0x017b 4015#define mmPA_CL_UCP_3_X_BASE_IDX 1 4016#define mmPA_CL_UCP_3_Y 0x017c 4017#define mmPA_CL_UCP_3_Y_BASE_IDX 1 4018#define mmPA_CL_UCP_3_Z 0x017d 4019#define mmPA_CL_UCP_3_Z_BASE_IDX 1 4020#define mmPA_CL_UCP_3_W 0x017e 4021#define mmPA_CL_UCP_3_W_BASE_IDX 1 4022#define mmPA_CL_UCP_4_X 0x017f 4023#define mmPA_CL_UCP_4_X_BASE_IDX 1 4024#define mmPA_CL_UCP_4_Y 0x0180 4025#define mmPA_CL_UCP_4_Y_BASE_IDX 1 4026#define mmPA_CL_UCP_4_Z 0x0181 4027#define mmPA_CL_UCP_4_Z_BASE_IDX 1 4028#define mmPA_CL_UCP_4_W 0x0182 4029#define mmPA_CL_UCP_4_W_BASE_IDX 1 4030#define mmPA_CL_UCP_5_X 0x0183 4031#define mmPA_CL_UCP_5_X_BASE_IDX 1 4032#define mmPA_CL_UCP_5_Y 0x0184 4033#define mmPA_CL_UCP_5_Y_BASE_IDX 1 4034#define mmPA_CL_UCP_5_Z 0x0185 4035#define mmPA_CL_UCP_5_Z_BASE_IDX 1 4036#define mmPA_CL_UCP_5_W 0x0186 4037#define mmPA_CL_UCP_5_W_BASE_IDX 1 4038#define mmPA_CL_PROG_NEAR_CLIP_Z 0x0187 4039#define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 4040#define mmSPI_PS_INPUT_CNTL_0 0x0191 4041#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 4042#define mmSPI_PS_INPUT_CNTL_1 0x0192 4043#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 4044#define mmSPI_PS_INPUT_CNTL_2 0x0193 4045#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 4046#define mmSPI_PS_INPUT_CNTL_3 0x0194 4047#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 4048#define mmSPI_PS_INPUT_CNTL_4 0x0195 4049#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 4050#define mmSPI_PS_INPUT_CNTL_5 0x0196 4051#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 4052#define mmSPI_PS_INPUT_CNTL_6 0x0197 4053#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 4054#define mmSPI_PS_INPUT_CNTL_7 0x0198 4055#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 4056#define mmSPI_PS_INPUT_CNTL_8 0x0199 4057#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 4058#define mmSPI_PS_INPUT_CNTL_9 0x019a 4059#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 4060#define mmSPI_PS_INPUT_CNTL_10 0x019b 4061#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 4062#define mmSPI_PS_INPUT_CNTL_11 0x019c 4063#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 4064#define mmSPI_PS_INPUT_CNTL_12 0x019d 4065#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 4066#define mmSPI_PS_INPUT_CNTL_13 0x019e 4067#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 4068#define mmSPI_PS_INPUT_CNTL_14 0x019f 4069#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 4070#define mmSPI_PS_INPUT_CNTL_15 0x01a0 4071#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 4072#define mmSPI_PS_INPUT_CNTL_16 0x01a1 4073#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 4074#define mmSPI_PS_INPUT_CNTL_17 0x01a2 4075#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 4076#define mmSPI_PS_INPUT_CNTL_18 0x01a3 4077#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 4078#define mmSPI_PS_INPUT_CNTL_19 0x01a4 4079#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 4080#define mmSPI_PS_INPUT_CNTL_20 0x01a5 4081#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 4082#define mmSPI_PS_INPUT_CNTL_21 0x01a6 4083#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 4084#define mmSPI_PS_INPUT_CNTL_22 0x01a7 4085#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 4086#define mmSPI_PS_INPUT_CNTL_23 0x01a8 4087#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 4088#define mmSPI_PS_INPUT_CNTL_24 0x01a9 4089#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 4090#define mmSPI_PS_INPUT_CNTL_25 0x01aa 4091#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 4092#define mmSPI_PS_INPUT_CNTL_26 0x01ab 4093#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 4094#define mmSPI_PS_INPUT_CNTL_27 0x01ac 4095#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 4096#define mmSPI_PS_INPUT_CNTL_28 0x01ad 4097#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 4098#define mmSPI_PS_INPUT_CNTL_29 0x01ae 4099#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 4100#define mmSPI_PS_INPUT_CNTL_30 0x01af 4101#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 4102#define mmSPI_PS_INPUT_CNTL_31 0x01b0 4103#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 4104#define mmSPI_VS_OUT_CONFIG 0x01b1 4105#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 4106#define mmSPI_PS_INPUT_ENA 0x01b3 4107#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 4108#define mmSPI_PS_INPUT_ADDR 0x01b4 4109#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 4110#define mmSPI_INTERP_CONTROL_0 0x01b5 4111#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 4112#define mmSPI_PS_IN_CONTROL 0x01b6 4113#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 4114#define mmSPI_BARYC_CNTL 0x01b8 4115#define mmSPI_BARYC_CNTL_BASE_IDX 1 4116#define mmSPI_TMPRING_SIZE 0x01ba 4117#define mmSPI_TMPRING_SIZE_BASE_IDX 1 4118#define mmSPI_SHADER_POS_FORMAT 0x01c3 4119#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 4120#define mmSPI_SHADER_Z_FORMAT 0x01c4 4121#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 4122#define mmSPI_SHADER_COL_FORMAT 0x01c5 4123#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 4124#define mmSX_PS_DOWNCONVERT 0x01d5 4125#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 4126#define mmSX_BLEND_OPT_EPSILON 0x01d6 4127#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 4128#define mmSX_BLEND_OPT_CONTROL 0x01d7 4129#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 4130#define mmSX_MRT0_BLEND_OPT 0x01d8 4131#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 4132#define mmSX_MRT1_BLEND_OPT 0x01d9 4133#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 4134#define mmSX_MRT2_BLEND_OPT 0x01da 4135#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 4136#define mmSX_MRT3_BLEND_OPT 0x01db 4137#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 4138#define mmSX_MRT4_BLEND_OPT 0x01dc 4139#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 4140#define mmSX_MRT5_BLEND_OPT 0x01dd 4141#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 4142#define mmSX_MRT6_BLEND_OPT 0x01de 4143#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 4144#define mmSX_MRT7_BLEND_OPT 0x01df 4145#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 4146#define mmCB_BLEND0_CONTROL 0x01e0 4147#define mmCB_BLEND0_CONTROL_BASE_IDX 1 4148#define mmCB_BLEND1_CONTROL 0x01e1 4149#define mmCB_BLEND1_CONTROL_BASE_IDX 1 4150#define mmCB_BLEND2_CONTROL 0x01e2 4151#define mmCB_BLEND2_CONTROL_BASE_IDX 1 4152#define mmCB_BLEND3_CONTROL 0x01e3 4153#define mmCB_BLEND3_CONTROL_BASE_IDX 1 4154#define mmCB_BLEND4_CONTROL 0x01e4 4155#define mmCB_BLEND4_CONTROL_BASE_IDX 1 4156#define mmCB_BLEND5_CONTROL 0x01e5 4157#define mmCB_BLEND5_CONTROL_BASE_IDX 1 4158#define mmCB_BLEND6_CONTROL 0x01e6 4159#define mmCB_BLEND6_CONTROL_BASE_IDX 1 4160#define mmCB_BLEND7_CONTROL 0x01e7 4161#define mmCB_BLEND7_CONTROL_BASE_IDX 1 4162#define mmCB_MRT0_EPITCH 0x01e8 4163#define mmCB_MRT0_EPITCH_BASE_IDX 1 4164#define mmCB_MRT1_EPITCH 0x01e9 4165#define mmCB_MRT1_EPITCH_BASE_IDX 1 4166#define mmCB_MRT2_EPITCH 0x01ea 4167#define mmCB_MRT2_EPITCH_BASE_IDX 1 4168#define mmCB_MRT3_EPITCH 0x01eb 4169#define mmCB_MRT3_EPITCH_BASE_IDX 1 4170#define mmCB_MRT4_EPITCH 0x01ec 4171#define mmCB_MRT4_EPITCH_BASE_IDX 1 4172#define mmCB_MRT5_EPITCH 0x01ed 4173#define mmCB_MRT5_EPITCH_BASE_IDX 1 4174#define mmCB_MRT6_EPITCH 0x01ee 4175#define mmCB_MRT6_EPITCH_BASE_IDX 1 4176#define mmCB_MRT7_EPITCH 0x01ef 4177#define mmCB_MRT7_EPITCH_BASE_IDX 1 4178#define mmCS_COPY_STATE 0x01f3 4179#define mmCS_COPY_STATE_BASE_IDX 1 4180#define mmGFX_COPY_STATE 0x01f4 4181#define mmGFX_COPY_STATE_BASE_IDX 1 4182#define mmPA_CL_POINT_X_RAD 0x01f5 4183#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 4184#define mmPA_CL_POINT_Y_RAD 0x01f6 4185#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 4186#define mmPA_CL_POINT_SIZE 0x01f7 4187#define mmPA_CL_POINT_SIZE_BASE_IDX 1 4188#define mmPA_CL_POINT_CULL_RAD 0x01f8 4189#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 4190#define mmVGT_DMA_BASE_HI 0x01f9 4191#define mmVGT_DMA_BASE_HI_BASE_IDX 1 4192#define mmVGT_DMA_BASE 0x01fa 4193#define mmVGT_DMA_BASE_BASE_IDX 1 4194#define mmVGT_DRAW_INITIATOR 0x01fc 4195#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 4196#define mmVGT_IMMED_DATA 0x01fd 4197#define mmVGT_IMMED_DATA_BASE_IDX 1 4198#define mmVGT_EVENT_ADDRESS_REG 0x01fe 4199#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 4200#define mmDB_DEPTH_CONTROL 0x0200 4201#define mmDB_DEPTH_CONTROL_BASE_IDX 1 4202#define mmDB_EQAA 0x0201 4203#define mmDB_EQAA_BASE_IDX 1 4204#define mmCB_COLOR_CONTROL 0x0202 4205#define mmCB_COLOR_CONTROL_BASE_IDX 1 4206#define mmDB_SHADER_CONTROL 0x0203 4207#define mmDB_SHADER_CONTROL_BASE_IDX 1 4208#define mmPA_CL_CLIP_CNTL 0x0204 4209#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 4210#define mmPA_SU_SC_MODE_CNTL 0x0205 4211#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 4212#define mmPA_CL_VTE_CNTL 0x0206 4213#define mmPA_CL_VTE_CNTL_BASE_IDX 1 4214#define mmPA_CL_VS_OUT_CNTL 0x0207 4215#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 4216#define mmPA_CL_NANINF_CNTL 0x0208 4217#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 4218#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 4219#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 4220#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a 4221#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 4222#define mmPA_SU_PRIM_FILTER_CNTL 0x020b 4223#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 4224#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 4225#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 4226#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d 4227#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 4228#define mmPA_CL_NGG_CNTL 0x020e 4229#define mmPA_CL_NGG_CNTL_BASE_IDX 1 4230#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f 4231#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 4232#define mmPA_STEREO_CNTL 0x0210 4233#define mmPA_STEREO_CNTL_BASE_IDX 1 4234#define mmPA_SU_POINT_SIZE 0x0280 4235#define mmPA_SU_POINT_SIZE_BASE_IDX 1 4236#define mmPA_SU_POINT_MINMAX 0x0281 4237#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 4238#define mmPA_SU_LINE_CNTL 0x0282 4239#define mmPA_SU_LINE_CNTL_BASE_IDX 1 4240#define mmPA_SC_LINE_STIPPLE 0x0283 4241#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 4242#define mmVGT_OUTPUT_PATH_CNTL 0x0284 4243#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 4244#define mmVGT_HOS_CNTL 0x0285 4245#define mmVGT_HOS_CNTL_BASE_IDX 1 4246#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 4247#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 4248#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 4249#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 4250#define mmVGT_HOS_REUSE_DEPTH 0x0288 4251#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 4252#define mmVGT_GROUP_PRIM_TYPE 0x0289 4253#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 4254#define mmVGT_GROUP_FIRST_DECR 0x028a 4255#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 4256#define mmVGT_GROUP_DECR 0x028b 4257#define mmVGT_GROUP_DECR_BASE_IDX 1 4258#define mmVGT_GROUP_VECT_0_CNTL 0x028c 4259#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 4260#define mmVGT_GROUP_VECT_1_CNTL 0x028d 4261#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 4262#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e 4263#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 4264#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f 4265#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 4266#define mmVGT_GS_MODE 0x0290 4267#define mmVGT_GS_MODE_BASE_IDX 1 4268#define mmVGT_GS_ONCHIP_CNTL 0x0291 4269#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 4270#define mmPA_SC_MODE_CNTL_0 0x0292 4271#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 4272#define mmPA_SC_MODE_CNTL_1 0x0293 4273#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 4274#define mmVGT_ENHANCE 0x0294 4275#define mmVGT_ENHANCE_BASE_IDX 1 4276#define mmVGT_GS_PER_ES 0x0295 4277#define mmVGT_GS_PER_ES_BASE_IDX 1 4278#define mmVGT_ES_PER_GS 0x0296 4279#define mmVGT_ES_PER_GS_BASE_IDX 1 4280#define mmVGT_GS_PER_VS 0x0297 4281#define mmVGT_GS_PER_VS_BASE_IDX 1 4282#define mmVGT_GSVS_RING_OFFSET_1 0x0298 4283#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 4284#define mmVGT_GSVS_RING_OFFSET_2 0x0299 4285#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 4286#define mmVGT_GSVS_RING_OFFSET_3 0x029a 4287#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 4288#define mmVGT_GS_OUT_PRIM_TYPE 0x029b 4289#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 4290#define mmIA_ENHANCE 0x029c 4291#define mmIA_ENHANCE_BASE_IDX 1 4292#define mmVGT_DMA_SIZE 0x029d 4293#define mmVGT_DMA_SIZE_BASE_IDX 1 4294#define mmVGT_DMA_MAX_SIZE 0x029e 4295#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 4296#define mmVGT_DMA_INDEX_TYPE 0x029f 4297#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 4298#define mmWD_ENHANCE 0x02a0 4299#define mmWD_ENHANCE_BASE_IDX 1 4300#define mmVGT_PRIMITIVEID_EN 0x02a1 4301#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 4302#define mmVGT_DMA_NUM_INSTANCES 0x02a2 4303#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 4304#define mmVGT_PRIMITIVEID_RESET 0x02a3 4305#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 4306#define mmVGT_EVENT_INITIATOR 0x02a4 4307#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 4308#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 4309#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4310#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 4311#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4312#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 4313#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4314#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 4315#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 4316#define mmIA_MULTI_VGT_PARAM_BC 0x02aa 4317#define mmIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 4318#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab 4319#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 4320#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac 4321#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 4322#define mmVGT_REUSE_OFF 0x02ad 4323#define mmVGT_REUSE_OFF_BASE_IDX 1 4324#define mmVGT_VTX_CNT_EN 0x02ae 4325#define mmVGT_VTX_CNT_EN_BASE_IDX 1 4326#define mmDB_HTILE_SURFACE 0x02af 4327#define mmDB_HTILE_SURFACE_BASE_IDX 1 4328#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 4329#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 4330#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 4331#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 4332#define mmDB_PRELOAD_CONTROL 0x02b2 4333#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 4334#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 4335#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 4336#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 4337#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 4338#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 4339#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 4340#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 4341#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 4342#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 4343#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 4344#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb 4345#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 4346#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc 4347#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 4348#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd 4349#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 4350#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf 4351#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 4352#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 4353#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 4354#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 4355#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 4356#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 4357#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 4358#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 4359#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 4360#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 4361#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 4362#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 4363#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 4364#define mmVGT_GS_MAX_VERT_OUT 0x02ce 4365#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 4366#define mmVGT_TESS_DISTRIBUTION 0x02d4 4367#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 4368#define mmVGT_SHADER_STAGES_EN 0x02d5 4369#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 4370#define mmVGT_LS_HS_CONFIG 0x02d6 4371#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 4372#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 4373#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 4374#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 4375#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 4376#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 4377#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 4378#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da 4379#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 4380#define mmVGT_TF_PARAM 0x02db 4381#define mmVGT_TF_PARAM_BASE_IDX 1 4382#define mmDB_ALPHA_TO_MASK 0x02dc 4383#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 4384#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd 4385#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 4386#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 4387#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 4388#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df 4389#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 4390#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 4391#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 4392#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 4393#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 4394#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 4395#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 4396#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 4397#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 4398#define mmVGT_GS_INSTANCE_CNT 0x02e4 4399#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 4400#define mmVGT_STRMOUT_CONFIG 0x02e5 4401#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 4402#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 4403#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 4404#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 4405#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 4406#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 4407#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 4408#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 4409#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 4410#define mmPA_SC_LINE_CNTL 0x02f7 4411#define mmPA_SC_LINE_CNTL_BASE_IDX 1 4412#define mmPA_SC_AA_CONFIG 0x02f8 4413#define mmPA_SC_AA_CONFIG_BASE_IDX 1 4414#define mmPA_SU_VTX_CNTL 0x02f9 4415#define mmPA_SU_VTX_CNTL_BASE_IDX 1 4416#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa 4417#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 4418#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb 4419#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 4420#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 4421#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 4422#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd 4423#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 4424#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 4425#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 4426#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 4427#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 4428#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 4429#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 4430#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 4431#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 4432#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 4433#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 4434#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 4435#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 4436#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 4437#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 4438#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 4439#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 4440#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 4441#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 4442#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 4443#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 4444#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 4445#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 4446#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 4447#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 4448#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 4449#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 4450#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 4451#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 4452#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 4453#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 4454#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 4455#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 4456#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 4457#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 4458#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 4459#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 4460#define mmPA_SC_SHADER_CONTROL 0x0310 4461#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 4462#define mmPA_SC_BINNER_CNTL_0 0x0311 4463#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 4464#define mmPA_SC_BINNER_CNTL_1 0x0312 4465#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 4466#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 4467#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 4468#define mmPA_SC_NGG_MODE_CNTL 0x0314 4469#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 4470#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 4471#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 4472#define mmVGT_OUT_DEALLOC_CNTL 0x0317 4473#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 4474#define mmCB_COLOR0_BASE 0x0318 4475#define mmCB_COLOR0_BASE_BASE_IDX 1 4476#define mmCB_COLOR0_BASE_EXT 0x0319 4477#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 4478#define mmCB_COLOR0_ATTRIB2 0x031a 4479#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 4480#define mmCB_COLOR0_VIEW 0x031b 4481#define mmCB_COLOR0_VIEW_BASE_IDX 1 4482#define mmCB_COLOR0_INFO 0x031c 4483#define mmCB_COLOR0_INFO_BASE_IDX 1 4484#define mmCB_COLOR0_ATTRIB 0x031d 4485#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 4486#define mmCB_COLOR0_DCC_CONTROL 0x031e 4487#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 4488#define mmCB_COLOR0_CMASK 0x031f 4489#define mmCB_COLOR0_CMASK_BASE_IDX 1 4490#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320 4491#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 4492#define mmCB_COLOR0_FMASK 0x0321 4493#define mmCB_COLOR0_FMASK_BASE_IDX 1 4494#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322 4495#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 4496#define mmCB_COLOR0_CLEAR_WORD0 0x0323 4497#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 4498#define mmCB_COLOR0_CLEAR_WORD1 0x0324 4499#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 4500#define mmCB_COLOR0_DCC_BASE 0x0325 4501#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 4502#define mmCB_COLOR0_DCC_BASE_EXT 0x0326 4503#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 4504#define mmCB_COLOR1_BASE 0x0327 4505#define mmCB_COLOR1_BASE_BASE_IDX 1 4506#define mmCB_COLOR1_BASE_EXT 0x0328 4507#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 4508#define mmCB_COLOR1_ATTRIB2 0x0329 4509#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 4510#define mmCB_COLOR1_VIEW 0x032a 4511#define mmCB_COLOR1_VIEW_BASE_IDX 1 4512#define mmCB_COLOR1_INFO 0x032b 4513#define mmCB_COLOR1_INFO_BASE_IDX 1 4514#define mmCB_COLOR1_ATTRIB 0x032c 4515#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 4516#define mmCB_COLOR1_DCC_CONTROL 0x032d 4517#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 4518#define mmCB_COLOR1_CMASK 0x032e 4519#define mmCB_COLOR1_CMASK_BASE_IDX 1 4520#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f 4521#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 4522#define mmCB_COLOR1_FMASK 0x0330 4523#define mmCB_COLOR1_FMASK_BASE_IDX 1 4524#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331 4525#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 4526#define mmCB_COLOR1_CLEAR_WORD0 0x0332 4527#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 4528#define mmCB_COLOR1_CLEAR_WORD1 0x0333 4529#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 4530#define mmCB_COLOR1_DCC_BASE 0x0334 4531#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 4532#define mmCB_COLOR1_DCC_BASE_EXT 0x0335 4533#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 4534#define mmCB_COLOR2_BASE 0x0336 4535#define mmCB_COLOR2_BASE_BASE_IDX 1 4536#define mmCB_COLOR2_BASE_EXT 0x0337 4537#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 4538#define mmCB_COLOR2_ATTRIB2 0x0338 4539#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 4540#define mmCB_COLOR2_VIEW 0x0339 4541#define mmCB_COLOR2_VIEW_BASE_IDX 1 4542#define mmCB_COLOR2_INFO 0x033a 4543#define mmCB_COLOR2_INFO_BASE_IDX 1 4544#define mmCB_COLOR2_ATTRIB 0x033b 4545#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 4546#define mmCB_COLOR2_DCC_CONTROL 0x033c 4547#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 4548#define mmCB_COLOR2_CMASK 0x033d 4549#define mmCB_COLOR2_CMASK_BASE_IDX 1 4550#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e 4551#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 4552#define mmCB_COLOR2_FMASK 0x033f 4553#define mmCB_COLOR2_FMASK_BASE_IDX 1 4554#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340 4555#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 4556#define mmCB_COLOR2_CLEAR_WORD0 0x0341 4557#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 4558#define mmCB_COLOR2_CLEAR_WORD1 0x0342 4559#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 4560#define mmCB_COLOR2_DCC_BASE 0x0343 4561#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 4562#define mmCB_COLOR2_DCC_BASE_EXT 0x0344 4563#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 4564#define mmCB_COLOR3_BASE 0x0345 4565#define mmCB_COLOR3_BASE_BASE_IDX 1 4566#define mmCB_COLOR3_BASE_EXT 0x0346 4567#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 4568#define mmCB_COLOR3_ATTRIB2 0x0347 4569#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 4570#define mmCB_COLOR3_VIEW 0x0348 4571#define mmCB_COLOR3_VIEW_BASE_IDX 1 4572#define mmCB_COLOR3_INFO 0x0349 4573#define mmCB_COLOR3_INFO_BASE_IDX 1 4574#define mmCB_COLOR3_ATTRIB 0x034a 4575#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 4576#define mmCB_COLOR3_DCC_CONTROL 0x034b 4577#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 4578#define mmCB_COLOR3_CMASK 0x034c 4579#define mmCB_COLOR3_CMASK_BASE_IDX 1 4580#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d 4581#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 4582#define mmCB_COLOR3_FMASK 0x034e 4583#define mmCB_COLOR3_FMASK_BASE_IDX 1 4584#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f 4585#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 4586#define mmCB_COLOR3_CLEAR_WORD0 0x0350 4587#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 4588#define mmCB_COLOR3_CLEAR_WORD1 0x0351 4589#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 4590#define mmCB_COLOR3_DCC_BASE 0x0352 4591#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 4592#define mmCB_COLOR3_DCC_BASE_EXT 0x0353 4593#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 4594#define mmCB_COLOR4_BASE 0x0354 4595#define mmCB_COLOR4_BASE_BASE_IDX 1 4596#define mmCB_COLOR4_BASE_EXT 0x0355 4597#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 4598#define mmCB_COLOR4_ATTRIB2 0x0356 4599#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 4600#define mmCB_COLOR4_VIEW 0x0357 4601#define mmCB_COLOR4_VIEW_BASE_IDX 1 4602#define mmCB_COLOR4_INFO 0x0358 4603#define mmCB_COLOR4_INFO_BASE_IDX 1 4604#define mmCB_COLOR4_ATTRIB 0x0359 4605#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 4606#define mmCB_COLOR4_DCC_CONTROL 0x035a 4607#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 4608#define mmCB_COLOR4_CMASK 0x035b 4609#define mmCB_COLOR4_CMASK_BASE_IDX 1 4610#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c 4611#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 4612#define mmCB_COLOR4_FMASK 0x035d 4613#define mmCB_COLOR4_FMASK_BASE_IDX 1 4614#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e 4615#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 4616#define mmCB_COLOR4_CLEAR_WORD0 0x035f 4617#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 4618#define mmCB_COLOR4_CLEAR_WORD1 0x0360 4619#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 4620#define mmCB_COLOR4_DCC_BASE 0x0361 4621#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 4622#define mmCB_COLOR4_DCC_BASE_EXT 0x0362 4623#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 4624#define mmCB_COLOR5_BASE 0x0363 4625#define mmCB_COLOR5_BASE_BASE_IDX 1 4626#define mmCB_COLOR5_BASE_EXT 0x0364 4627#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 4628#define mmCB_COLOR5_ATTRIB2 0x0365 4629#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 4630#define mmCB_COLOR5_VIEW 0x0366 4631#define mmCB_COLOR5_VIEW_BASE_IDX 1 4632#define mmCB_COLOR5_INFO 0x0367 4633#define mmCB_COLOR5_INFO_BASE_IDX 1 4634#define mmCB_COLOR5_ATTRIB 0x0368 4635#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 4636#define mmCB_COLOR5_DCC_CONTROL 0x0369 4637#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 4638#define mmCB_COLOR5_CMASK 0x036a 4639#define mmCB_COLOR5_CMASK_BASE_IDX 1 4640#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b 4641#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 4642#define mmCB_COLOR5_FMASK 0x036c 4643#define mmCB_COLOR5_FMASK_BASE_IDX 1 4644#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d 4645#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 4646#define mmCB_COLOR5_CLEAR_WORD0 0x036e 4647#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 4648#define mmCB_COLOR5_CLEAR_WORD1 0x036f 4649#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 4650#define mmCB_COLOR5_DCC_BASE 0x0370 4651#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 4652#define mmCB_COLOR5_DCC_BASE_EXT 0x0371 4653#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 4654#define mmCB_COLOR6_BASE 0x0372 4655#define mmCB_COLOR6_BASE_BASE_IDX 1 4656#define mmCB_COLOR6_BASE_EXT 0x0373 4657#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 4658#define mmCB_COLOR6_ATTRIB2 0x0374 4659#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 4660#define mmCB_COLOR6_VIEW 0x0375 4661#define mmCB_COLOR6_VIEW_BASE_IDX 1 4662#define mmCB_COLOR6_INFO 0x0376 4663#define mmCB_COLOR6_INFO_BASE_IDX 1 4664#define mmCB_COLOR6_ATTRIB 0x0377 4665#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 4666#define mmCB_COLOR6_DCC_CONTROL 0x0378 4667#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 4668#define mmCB_COLOR6_CMASK 0x0379 4669#define mmCB_COLOR6_CMASK_BASE_IDX 1 4670#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a 4671#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 4672#define mmCB_COLOR6_FMASK 0x037b 4673#define mmCB_COLOR6_FMASK_BASE_IDX 1 4674#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c 4675#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 4676#define mmCB_COLOR6_CLEAR_WORD0 0x037d 4677#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 4678#define mmCB_COLOR6_CLEAR_WORD1 0x037e 4679#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 4680#define mmCB_COLOR6_DCC_BASE 0x037f 4681#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 4682#define mmCB_COLOR6_DCC_BASE_EXT 0x0380 4683#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 4684#define mmCB_COLOR7_BASE 0x0381 4685#define mmCB_COLOR7_BASE_BASE_IDX 1 4686#define mmCB_COLOR7_BASE_EXT 0x0382 4687#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 4688#define mmCB_COLOR7_ATTRIB2 0x0383 4689#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 4690#define mmCB_COLOR7_VIEW 0x0384 4691#define mmCB_COLOR7_VIEW_BASE_IDX 1 4692#define mmCB_COLOR7_INFO 0x0385 4693#define mmCB_COLOR7_INFO_BASE_IDX 1 4694#define mmCB_COLOR7_ATTRIB 0x0386 4695#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 4696#define mmCB_COLOR7_DCC_CONTROL 0x0387 4697#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 4698#define mmCB_COLOR7_CMASK 0x0388 4699#define mmCB_COLOR7_CMASK_BASE_IDX 1 4700#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389 4701#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 4702#define mmCB_COLOR7_FMASK 0x038a 4703#define mmCB_COLOR7_FMASK_BASE_IDX 1 4704#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b 4705#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 4706#define mmCB_COLOR7_CLEAR_WORD0 0x038c 4707#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 4708#define mmCB_COLOR7_CLEAR_WORD1 0x038d 4709#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 4710#define mmCB_COLOR7_DCC_BASE 0x038e 4711#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 4712#define mmCB_COLOR7_DCC_BASE_EXT 0x038f 4713#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 4714 4715 4716// addressBlock: gc_gfxudec 4717// base address: 0x30000 4718#define mmCP_EOP_DONE_ADDR_LO 0x2000 4719#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 4720#define mmCP_EOP_DONE_ADDR_HI 0x2001 4721#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 4722#define mmCP_EOP_DONE_DATA_LO 0x2002 4723#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 4724#define mmCP_EOP_DONE_DATA_HI 0x2003 4725#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 4726#define mmCP_EOP_LAST_FENCE_LO 0x2004 4727#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 4728#define mmCP_EOP_LAST_FENCE_HI 0x2005 4729#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 4730#define mmCP_STREAM_OUT_ADDR_LO 0x2006 4731#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 4732#define mmCP_STREAM_OUT_ADDR_HI 0x2007 4733#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 4734#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 4735#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 4736#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 4737#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 4738#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a 4739#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 4740#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b 4741#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 4742#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c 4743#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 4744#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d 4745#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 4746#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e 4747#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 4748#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f 4749#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 4750#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 4751#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 4752#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 4753#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 4754#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 4755#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 4756#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 4757#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 4758#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 4759#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 4760#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 4761#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 4762#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 4763#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 4764#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 4765#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 4766#define mmCP_PIPE_STATS_ADDR_LO 0x2018 4767#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 4768#define mmCP_PIPE_STATS_ADDR_HI 0x2019 4769#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 4770#define mmCP_VGT_IAVERT_COUNT_LO 0x201a 4771#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 4772#define mmCP_VGT_IAVERT_COUNT_HI 0x201b 4773#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 4774#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c 4775#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 4776#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d 4777#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 4778#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e 4779#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 4780#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f 4781#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 4782#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 4783#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 4784#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 4785#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 4786#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 4787#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 4788#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 4789#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 4790#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 4791#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 4792#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 4793#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 4794#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 4795#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 4796#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 4797#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 4798#define mmCP_PA_CINVOC_COUNT_LO 0x2028 4799#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 4800#define mmCP_PA_CINVOC_COUNT_HI 0x2029 4801#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 4802#define mmCP_PA_CPRIM_COUNT_LO 0x202a 4803#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 4804#define mmCP_PA_CPRIM_COUNT_HI 0x202b 4805#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 4806#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c 4807#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 4808#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d 4809#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 4810#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e 4811#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 4812#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f 4813#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 4814#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 4815#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 4816#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 4817#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 4818#define mmCP_PIPE_STATS_CONTROL 0x203d 4819#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 4820#define mmCP_STREAM_OUT_CONTROL 0x203e 4821#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 4822#define mmCP_STRMOUT_CNTL 0x203f 4823#define mmCP_STRMOUT_CNTL_BASE_IDX 1 4824#define mmSCRATCH_REG0 0x2040 4825#define mmSCRATCH_REG0_BASE_IDX 1 4826#define mmSCRATCH_REG1 0x2041 4827#define mmSCRATCH_REG1_BASE_IDX 1 4828#define mmSCRATCH_REG2 0x2042 4829#define mmSCRATCH_REG2_BASE_IDX 1 4830#define mmSCRATCH_REG3 0x2043 4831#define mmSCRATCH_REG3_BASE_IDX 1 4832#define mmSCRATCH_REG4 0x2044 4833#define mmSCRATCH_REG4_BASE_IDX 1 4834#define mmSCRATCH_REG5 0x2045 4835#define mmSCRATCH_REG5_BASE_IDX 1 4836#define mmSCRATCH_REG6 0x2046 4837#define mmSCRATCH_REG6_BASE_IDX 1 4838#define mmSCRATCH_REG7 0x2047 4839#define mmSCRATCH_REG7_BASE_IDX 1 4840#define mmCP_APPEND_DATA_HI 0x204c 4841#define mmCP_APPEND_DATA_HI_BASE_IDX 1 4842#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d 4843#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 4844#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e 4845#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 4846#define mmSCRATCH_UMSK 0x2050 4847#define mmSCRATCH_UMSK_BASE_IDX 1 4848#define mmSCRATCH_ADDR 0x2051 4849#define mmSCRATCH_ADDR_BASE_IDX 1 4850#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 4851#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 4852#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 4853#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 4854#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 4855#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4856#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 4857#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4858#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 4859#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4860#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 4861#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4862#define mmCP_APPEND_ADDR_LO 0x2058 4863#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 4864#define mmCP_APPEND_ADDR_HI 0x2059 4865#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 4866#define mmCP_APPEND_DATA_LO 0x205a 4867#define mmCP_APPEND_DATA_LO_BASE_IDX 1 4868#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b 4869#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 4870#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c 4871#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 4872#define mmCP_ATOMIC_PREOP_LO 0x205d 4873#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 4874#define mmCP_ME_ATOMIC_PREOP_LO 0x205d 4875#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 4876#define mmCP_ATOMIC_PREOP_HI 0x205e 4877#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 4878#define mmCP_ME_ATOMIC_PREOP_HI 0x205e 4879#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 4880#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f 4881#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4882#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 4883#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4884#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 4885#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4886#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 4887#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4888#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 4889#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4890#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 4891#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4892#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 4893#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4894#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 4895#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4896#define mmCP_ME_MC_WADDR_LO 0x2069 4897#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 4898#define mmCP_ME_MC_WADDR_HI 0x206a 4899#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 4900#define mmCP_ME_MC_WDATA_LO 0x206b 4901#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 4902#define mmCP_ME_MC_WDATA_HI 0x206c 4903#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 4904#define mmCP_ME_MC_RADDR_LO 0x206d 4905#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 4906#define mmCP_ME_MC_RADDR_HI 0x206e 4907#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 4908#define mmCP_SEM_WAIT_TIMER 0x206f 4909#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 4910#define mmCP_SIG_SEM_ADDR_LO 0x2070 4911#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 4912#define mmCP_SIG_SEM_ADDR_HI 0x2071 4913#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 4914#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 4915#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 4916#define mmCP_WAIT_SEM_ADDR_LO 0x2075 4917#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 4918#define mmCP_WAIT_SEM_ADDR_HI 0x2076 4919#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 4920#define mmCP_DMA_PFP_CONTROL 0x2077 4921#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 4922#define mmCP_DMA_ME_CONTROL 0x2078 4923#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 4924#define mmCP_COHER_BASE_HI 0x2079 4925#define mmCP_COHER_BASE_HI_BASE_IDX 1 4926#define mmCP_COHER_START_DELAY 0x207b 4927#define mmCP_COHER_START_DELAY_BASE_IDX 1 4928#define mmCP_COHER_CNTL 0x207c 4929#define mmCP_COHER_CNTL_BASE_IDX 1 4930#define mmCP_COHER_SIZE 0x207d 4931#define mmCP_COHER_SIZE_BASE_IDX 1 4932#define mmCP_COHER_BASE 0x207e 4933#define mmCP_COHER_BASE_BASE_IDX 1 4934#define mmCP_COHER_STATUS 0x207f 4935#define mmCP_COHER_STATUS_BASE_IDX 1 4936#define mmCP_DMA_ME_SRC_ADDR 0x2080 4937#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 4938#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 4939#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 4940#define mmCP_DMA_ME_DST_ADDR 0x2082 4941#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 4942#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 4943#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 4944#define mmCP_DMA_ME_COMMAND 0x2084 4945#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 4946#define mmCP_DMA_PFP_SRC_ADDR 0x2085 4947#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 4948#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 4949#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 4950#define mmCP_DMA_PFP_DST_ADDR 0x2087 4951#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 4952#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 4953#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 4954#define mmCP_DMA_PFP_COMMAND 0x2089 4955#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 4956#define mmCP_DMA_CNTL 0x208a 4957#define mmCP_DMA_CNTL_BASE_IDX 1 4958#define mmCP_DMA_READ_TAGS 0x208b 4959#define mmCP_DMA_READ_TAGS_BASE_IDX 1 4960#define mmCP_COHER_SIZE_HI 0x208c 4961#define mmCP_COHER_SIZE_HI_BASE_IDX 1 4962#define mmCP_PFP_IB_CONTROL 0x208d 4963#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 4964#define mmCP_PFP_LOAD_CONTROL 0x208e 4965#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 4966#define mmCP_SCRATCH_INDEX 0x208f 4967#define mmCP_SCRATCH_INDEX_BASE_IDX 1 4968#define mmCP_SCRATCH_DATA 0x2090 4969#define mmCP_SCRATCH_DATA_BASE_IDX 1 4970#define mmCP_RB_OFFSET 0x2091 4971#define mmCP_RB_OFFSET_BASE_IDX 1 4972#define mmCP_IB1_OFFSET 0x2092 4973#define mmCP_IB1_OFFSET_BASE_IDX 1 4974#define mmCP_IB2_OFFSET 0x2093 4975#define mmCP_IB2_OFFSET_BASE_IDX 1 4976#define mmCP_IB1_PREAMBLE_BEGIN 0x2094 4977#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 4978#define mmCP_IB1_PREAMBLE_END 0x2095 4979#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1 4980#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 4981#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 4982#define mmCP_IB2_PREAMBLE_END 0x2097 4983#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 4984#define mmCP_CE_IB1_OFFSET 0x2098 4985#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 4986#define mmCP_CE_IB2_OFFSET 0x2099 4987#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 4988#define mmCP_CE_COUNTER 0x209a 4989#define mmCP_CE_COUNTER_BASE_IDX 1 4990#define mmCP_CE_RB_OFFSET 0x209b 4991#define mmCP_CE_RB_OFFSET_BASE_IDX 1 4992#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd 4993#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 4994#define mmCP_CE_IB1_CMD_BUFSZ 0x20be 4995#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 4996#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf 4997#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 4998#define mmCP_IB1_CMD_BUFSZ 0x20c0 4999#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 5000#define mmCP_IB2_CMD_BUFSZ 0x20c1 5001#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 5002#define mmCP_ST_CMD_BUFSZ 0x20c2 5003#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 5004#define mmCP_CE_INIT_BASE_LO 0x20c3 5005#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 5006#define mmCP_CE_INIT_BASE_HI 0x20c4 5007#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 5008#define mmCP_CE_INIT_BUFSZ 0x20c5 5009#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 5010#define mmCP_CE_IB1_BASE_LO 0x20c6 5011#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 5012#define mmCP_CE_IB1_BASE_HI 0x20c7 5013#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 5014#define mmCP_CE_IB1_BUFSZ 0x20c8 5015#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 5016#define mmCP_CE_IB2_BASE_LO 0x20c9 5017#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 5018#define mmCP_CE_IB2_BASE_HI 0x20ca 5019#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 5020#define mmCP_CE_IB2_BUFSZ 0x20cb 5021#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 5022#define mmCP_IB1_BASE_LO 0x20cc 5023#define mmCP_IB1_BASE_LO_BASE_IDX 1 5024#define mmCP_IB1_BASE_HI 0x20cd 5025#define mmCP_IB1_BASE_HI_BASE_IDX 1 5026#define mmCP_IB1_BUFSZ 0x20ce 5027#define mmCP_IB1_BUFSZ_BASE_IDX 1 5028#define mmCP_IB2_BASE_LO 0x20cf 5029#define mmCP_IB2_BASE_LO_BASE_IDX 1 5030#define mmCP_IB2_BASE_HI 0x20d0 5031#define mmCP_IB2_BASE_HI_BASE_IDX 1 5032#define mmCP_IB2_BUFSZ 0x20d1 5033#define mmCP_IB2_BUFSZ_BASE_IDX 1 5034#define mmCP_ST_BASE_LO 0x20d2 5035#define mmCP_ST_BASE_LO_BASE_IDX 1 5036#define mmCP_ST_BASE_HI 0x20d3 5037#define mmCP_ST_BASE_HI_BASE_IDX 1 5038#define mmCP_ST_BUFSZ 0x20d4 5039#define mmCP_ST_BUFSZ_BASE_IDX 1 5040#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 5041#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 5042#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 5043#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 5044#define mmCP_EOP_DONE_CNTX_ID 0x20d7 5045#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 5046#define mmCP_PFP_COMPLETION_STATUS 0x20ec 5047#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 5048#define mmCP_CE_COMPLETION_STATUS 0x20ed 5049#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 5050#define mmCP_PRED_NOT_VISIBLE 0x20ee 5051#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 5052#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 5053#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 5054#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 5055#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 5056#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 5057#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 5058#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 5059#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 5060#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 5061#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 5062#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 5063#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 5064#define mmCP_DISPATCH_INDR_ADDR 0x20f6 5065#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 5066#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 5067#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 5068#define mmCP_INDEX_BASE_ADDR 0x20f8 5069#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 5070#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 5071#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 5072#define mmCP_INDEX_TYPE 0x20fa 5073#define mmCP_INDEX_TYPE_BASE_IDX 1 5074#define mmCP_GDS_BKUP_ADDR 0x20fb 5075#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 5076#define mmCP_GDS_BKUP_ADDR_HI 0x20fc 5077#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 5078#define mmCP_SAMPLE_STATUS 0x20fd 5079#define mmCP_SAMPLE_STATUS_BASE_IDX 1 5080#define mmCP_ME_COHER_CNTL 0x20fe 5081#define mmCP_ME_COHER_CNTL_BASE_IDX 1 5082#define mmCP_ME_COHER_SIZE 0x20ff 5083#define mmCP_ME_COHER_SIZE_BASE_IDX 1 5084#define mmCP_ME_COHER_SIZE_HI 0x2100 5085#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 5086#define mmCP_ME_COHER_BASE 0x2101 5087#define mmCP_ME_COHER_BASE_BASE_IDX 1 5088#define mmCP_ME_COHER_BASE_HI 0x2102 5089#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 5090#define mmCP_ME_COHER_STATUS 0x2103 5091#define mmCP_ME_COHER_STATUS_BASE_IDX 1 5092#define mmRLC_GPM_PERF_COUNT_0 0x2140 5093#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 5094#define mmRLC_GPM_PERF_COUNT_1 0x2141 5095#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 5096#define mmGRBM_GFX_INDEX 0x2200 5097#define mmGRBM_GFX_INDEX_BASE_IDX 1 5098#define mmVGT_GSVS_RING_SIZE 0x2241 5099#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1 5100#define mmVGT_PRIMITIVE_TYPE 0x2242 5101#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 5102#define mmVGT_INDEX_TYPE 0x2243 5103#define mmVGT_INDEX_TYPE_BASE_IDX 1 5104#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 5105#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 5106#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 5107#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 5108#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 5109#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 5110#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 5111#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 5112#define mmVGT_MAX_VTX_INDX 0x2248 5113#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 5114#define mmVGT_MIN_VTX_INDX 0x2249 5115#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 5116#define mmVGT_INDX_OFFSET 0x224a 5117#define mmVGT_INDX_OFFSET_BASE_IDX 1 5118#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b 5119#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 5120#define mmVGT_NUM_INDICES 0x224c 5121#define mmVGT_NUM_INDICES_BASE_IDX 1 5122#define mmVGT_NUM_INSTANCES 0x224d 5123#define mmVGT_NUM_INSTANCES_BASE_IDX 1 5124#define mmVGT_TF_RING_SIZE 0x224e 5125#define mmVGT_TF_RING_SIZE_BASE_IDX 1 5126#define mmVGT_HS_OFFCHIP_PARAM 0x224f 5127#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 5128#define mmVGT_TF_MEMORY_BASE 0x2250 5129#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1 5130#define mmVGT_TF_MEMORY_BASE_HI 0x2251 5131#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 5132#define mmWD_POS_BUF_BASE 0x2252 5133#define mmWD_POS_BUF_BASE_BASE_IDX 1 5134#define mmWD_POS_BUF_BASE_HI 0x2253 5135#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 5136#define mmWD_CNTL_SB_BUF_BASE 0x2254 5137#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 5138#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 5139#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 5140#define mmWD_INDEX_BUF_BASE 0x2256 5141#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 5142#define mmWD_INDEX_BUF_BASE_HI 0x2257 5143#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 5144#define mmIA_MULTI_VGT_PARAM 0x2258 5145#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 5146#define mmVGT_INSTANCE_BASE_ID 0x225a 5147#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 5148#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 5149#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 5150#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 5151#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 5152#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 5153#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 5154#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 5155#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 5156#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 5157#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 5158#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b 5159#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 5160#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 5161#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5162#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 5163#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 5164#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 5165#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 5166#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 5167#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5168#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 5169#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5170#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 5171#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5172#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 5173#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 5174#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 5175#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 5176#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 5177#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5178#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 5179#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5180#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 5181#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 5182#define mmPA_SC_TRAP_SCREEN_H 0x22b1 5183#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 5184#define mmPA_SC_TRAP_SCREEN_V 0x22b2 5185#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 5186#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 5187#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5188#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 5189#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 5190#define mmPA_STATE_STEREO_X 0x22b5 5191#define mmPA_STATE_STEREO_X_BASE_IDX 1 5192#define mmSQ_THREAD_TRACE_BASE 0x2330 5193#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1 5194#define mmSQ_THREAD_TRACE_SIZE 0x2331 5195#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1 5196#define mmSQ_THREAD_TRACE_MASK 0x2332 5197#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1 5198#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333 5199#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 5200#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334 5201#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 5202#define mmSQ_THREAD_TRACE_CTRL 0x2335 5203#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1 5204#define mmSQ_THREAD_TRACE_MODE 0x2336 5205#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1 5206#define mmSQ_THREAD_TRACE_BASE2 0x2337 5207#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1 5208#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 5209#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 5210#define mmSQ_THREAD_TRACE_WPTR 0x2339 5211#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1 5212#define mmSQ_THREAD_TRACE_STATUS 0x233a 5213#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1 5214#define mmSQ_THREAD_TRACE_HIWATER 0x233b 5215#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 5216#define mmSQ_THREAD_TRACE_CNTR 0x233c 5217#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1 5218#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 5219#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 5220#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 5221#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 5222#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 5223#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 5224#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 5225#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 5226#define mmSQC_CACHES 0x2348 5227#define mmSQC_CACHES_BASE_IDX 1 5228#define mmSQC_WRITEBACK 0x2349 5229#define mmSQC_WRITEBACK_BASE_IDX 1 5230#define mmTA_CS_BC_BASE_ADDR 0x2380 5231#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 5232#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 5233#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 5234#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 5235#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 5236#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 5237#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 5238#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 5239#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 5240#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 5241#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 5242#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 5243#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 5244#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 5245#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 5246#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 5247#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 5248#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 5249#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 5250#define mmDB_ZPASS_COUNT_LOW 0x23fe 5251#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 5252#define mmDB_ZPASS_COUNT_HI 0x23ff 5253#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 5254#define mmGDS_RD_ADDR 0x2400 5255#define mmGDS_RD_ADDR_BASE_IDX 1 5256#define mmGDS_RD_DATA 0x2401 5257#define mmGDS_RD_DATA_BASE_IDX 1 5258#define mmGDS_RD_BURST_ADDR 0x2402 5259#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 5260#define mmGDS_RD_BURST_COUNT 0x2403 5261#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 5262#define mmGDS_RD_BURST_DATA 0x2404 5263#define mmGDS_RD_BURST_DATA_BASE_IDX 1 5264#define mmGDS_WR_ADDR 0x2405 5265#define mmGDS_WR_ADDR_BASE_IDX 1 5266#define mmGDS_WR_DATA 0x2406 5267#define mmGDS_WR_DATA_BASE_IDX 1 5268#define mmGDS_WR_BURST_ADDR 0x2407 5269#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 5270#define mmGDS_WR_BURST_DATA 0x2408 5271#define mmGDS_WR_BURST_DATA_BASE_IDX 1 5272#define mmGDS_WRITE_COMPLETE 0x2409 5273#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 5274#define mmGDS_ATOM_CNTL 0x240a 5275#define mmGDS_ATOM_CNTL_BASE_IDX 1 5276#define mmGDS_ATOM_COMPLETE 0x240b 5277#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 5278#define mmGDS_ATOM_BASE 0x240c 5279#define mmGDS_ATOM_BASE_BASE_IDX 1 5280#define mmGDS_ATOM_SIZE 0x240d 5281#define mmGDS_ATOM_SIZE_BASE_IDX 1 5282#define mmGDS_ATOM_OFFSET0 0x240e 5283#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 5284#define mmGDS_ATOM_OFFSET1 0x240f 5285#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 5286#define mmGDS_ATOM_DST 0x2410 5287#define mmGDS_ATOM_DST_BASE_IDX 1 5288#define mmGDS_ATOM_OP 0x2411 5289#define mmGDS_ATOM_OP_BASE_IDX 1 5290#define mmGDS_ATOM_SRC0 0x2412 5291#define mmGDS_ATOM_SRC0_BASE_IDX 1 5292#define mmGDS_ATOM_SRC0_U 0x2413 5293#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 5294#define mmGDS_ATOM_SRC1 0x2414 5295#define mmGDS_ATOM_SRC1_BASE_IDX 1 5296#define mmGDS_ATOM_SRC1_U 0x2415 5297#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 5298#define mmGDS_ATOM_READ0 0x2416 5299#define mmGDS_ATOM_READ0_BASE_IDX 1 5300#define mmGDS_ATOM_READ0_U 0x2417 5301#define mmGDS_ATOM_READ0_U_BASE_IDX 1 5302#define mmGDS_ATOM_READ1 0x2418 5303#define mmGDS_ATOM_READ1_BASE_IDX 1 5304#define mmGDS_ATOM_READ1_U 0x2419 5305#define mmGDS_ATOM_READ1_U_BASE_IDX 1 5306#define mmGDS_GWS_RESOURCE_CNTL 0x241a 5307#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 5308#define mmGDS_GWS_RESOURCE 0x241b 5309#define mmGDS_GWS_RESOURCE_BASE_IDX 1 5310#define mmGDS_GWS_RESOURCE_CNT 0x241c 5311#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 5312#define mmGDS_OA_CNTL 0x241d 5313#define mmGDS_OA_CNTL_BASE_IDX 1 5314#define mmGDS_OA_COUNTER 0x241e 5315#define mmGDS_OA_COUNTER_BASE_IDX 1 5316#define mmGDS_OA_ADDRESS 0x241f 5317#define mmGDS_OA_ADDRESS_BASE_IDX 1 5318#define mmGDS_OA_INCDEC 0x2420 5319#define mmGDS_OA_INCDEC_BASE_IDX 1 5320#define mmGDS_OA_RING_SIZE 0x2421 5321#define mmGDS_OA_RING_SIZE_BASE_IDX 1 5322#define mmSPI_CONFIG_CNTL 0x2440 5323#define mmSPI_CONFIG_CNTL_BASE_IDX 1 5324#define mmSPI_CONFIG_CNTL_1 0x2441 5325#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1 5326#define mmSPI_CONFIG_CNTL_2 0x2442 5327#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1 5328#define mmSPI_WAVE_LIMIT_CNTL 0x2443 5329#define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 5330 5331 5332// addressBlock: gc_perfddec 5333// base address: 0x34000 5334#define mmCPG_PERFCOUNTER1_LO 0x3000 5335#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 5336#define mmCPG_PERFCOUNTER1_HI 0x3001 5337#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 5338#define mmCPG_PERFCOUNTER0_LO 0x3002 5339#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 5340#define mmCPG_PERFCOUNTER0_HI 0x3003 5341#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 5342#define mmCPC_PERFCOUNTER1_LO 0x3004 5343#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 5344#define mmCPC_PERFCOUNTER1_HI 0x3005 5345#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 5346#define mmCPC_PERFCOUNTER0_LO 0x3006 5347#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 5348#define mmCPC_PERFCOUNTER0_HI 0x3007 5349#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 5350#define mmCPF_PERFCOUNTER1_LO 0x3008 5351#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 5352#define mmCPF_PERFCOUNTER1_HI 0x3009 5353#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 5354#define mmCPF_PERFCOUNTER0_LO 0x300a 5355#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 5356#define mmCPF_PERFCOUNTER0_HI 0x300b 5357#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 5358#define mmCPF_LATENCY_STATS_DATA 0x300c 5359#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 5360#define mmCPG_LATENCY_STATS_DATA 0x300d 5361#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 5362#define mmCPC_LATENCY_STATS_DATA 0x300e 5363#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 5364#define mmGRBM_PERFCOUNTER0_LO 0x3040 5365#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 5366#define mmGRBM_PERFCOUNTER0_HI 0x3041 5367#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 5368#define mmGRBM_PERFCOUNTER1_LO 0x3043 5369#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 5370#define mmGRBM_PERFCOUNTER1_HI 0x3044 5371#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 5372#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 5373#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 5374#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 5375#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 5376#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 5377#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 5378#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 5379#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 5380#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 5381#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 5382#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a 5383#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 5384#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b 5385#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 5386#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c 5387#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 5388#define mmWD_PERFCOUNTER0_LO 0x3080 5389#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1 5390#define mmWD_PERFCOUNTER0_HI 0x3081 5391#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1 5392#define mmWD_PERFCOUNTER1_LO 0x3082 5393#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1 5394#define mmWD_PERFCOUNTER1_HI 0x3083 5395#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1 5396#define mmWD_PERFCOUNTER2_LO 0x3084 5397#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1 5398#define mmWD_PERFCOUNTER2_HI 0x3085 5399#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1 5400#define mmWD_PERFCOUNTER3_LO 0x3086 5401#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1 5402#define mmWD_PERFCOUNTER3_HI 0x3087 5403#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1 5404#define mmIA_PERFCOUNTER0_LO 0x3088 5405#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1 5406#define mmIA_PERFCOUNTER0_HI 0x3089 5407#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1 5408#define mmIA_PERFCOUNTER1_LO 0x308a 5409#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1 5410#define mmIA_PERFCOUNTER1_HI 0x308b 5411#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1 5412#define mmIA_PERFCOUNTER2_LO 0x308c 5413#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1 5414#define mmIA_PERFCOUNTER2_HI 0x308d 5415#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1 5416#define mmIA_PERFCOUNTER3_LO 0x308e 5417#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1 5418#define mmIA_PERFCOUNTER3_HI 0x308f 5419#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1 5420#define mmVGT_PERFCOUNTER0_LO 0x3090 5421#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1 5422#define mmVGT_PERFCOUNTER0_HI 0x3091 5423#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1 5424#define mmVGT_PERFCOUNTER1_LO 0x3092 5425#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1 5426#define mmVGT_PERFCOUNTER1_HI 0x3093 5427#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1 5428#define mmVGT_PERFCOUNTER2_LO 0x3094 5429#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1 5430#define mmVGT_PERFCOUNTER2_HI 0x3095 5431#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1 5432#define mmVGT_PERFCOUNTER3_LO 0x3096 5433#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1 5434#define mmVGT_PERFCOUNTER3_HI 0x3097 5435#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1 5436#define mmPA_SU_PERFCOUNTER0_LO 0x3100 5437#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 5438#define mmPA_SU_PERFCOUNTER0_HI 0x3101 5439#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 5440#define mmPA_SU_PERFCOUNTER1_LO 0x3102 5441#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 5442#define mmPA_SU_PERFCOUNTER1_HI 0x3103 5443#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 5444#define mmPA_SU_PERFCOUNTER2_LO 0x3104 5445#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 5446#define mmPA_SU_PERFCOUNTER2_HI 0x3105 5447#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 5448#define mmPA_SU_PERFCOUNTER3_LO 0x3106 5449#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 5450#define mmPA_SU_PERFCOUNTER3_HI 0x3107 5451#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 5452#define mmPA_SC_PERFCOUNTER0_LO 0x3140 5453#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 5454#define mmPA_SC_PERFCOUNTER0_HI 0x3141 5455#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 5456#define mmPA_SC_PERFCOUNTER1_LO 0x3142 5457#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 5458#define mmPA_SC_PERFCOUNTER1_HI 0x3143 5459#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 5460#define mmPA_SC_PERFCOUNTER2_LO 0x3144 5461#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 5462#define mmPA_SC_PERFCOUNTER2_HI 0x3145 5463#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 5464#define mmPA_SC_PERFCOUNTER3_LO 0x3146 5465#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 5466#define mmPA_SC_PERFCOUNTER3_HI 0x3147 5467#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 5468#define mmPA_SC_PERFCOUNTER4_LO 0x3148 5469#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 5470#define mmPA_SC_PERFCOUNTER4_HI 0x3149 5471#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 5472#define mmPA_SC_PERFCOUNTER5_LO 0x314a 5473#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 5474#define mmPA_SC_PERFCOUNTER5_HI 0x314b 5475#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 5476#define mmPA_SC_PERFCOUNTER6_LO 0x314c 5477#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 5478#define mmPA_SC_PERFCOUNTER6_HI 0x314d 5479#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 5480#define mmPA_SC_PERFCOUNTER7_LO 0x314e 5481#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 5482#define mmPA_SC_PERFCOUNTER7_HI 0x314f 5483#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 5484#define mmSPI_PERFCOUNTER0_HI 0x3180 5485#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 5486#define mmSPI_PERFCOUNTER0_LO 0x3181 5487#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 5488#define mmSPI_PERFCOUNTER1_HI 0x3182 5489#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 5490#define mmSPI_PERFCOUNTER1_LO 0x3183 5491#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 5492#define mmSPI_PERFCOUNTER2_HI 0x3184 5493#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 5494#define mmSPI_PERFCOUNTER2_LO 0x3185 5495#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 5496#define mmSPI_PERFCOUNTER3_HI 0x3186 5497#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 5498#define mmSPI_PERFCOUNTER3_LO 0x3187 5499#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 5500#define mmSPI_PERFCOUNTER4_HI 0x3188 5501#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 5502#define mmSPI_PERFCOUNTER4_LO 0x3189 5503#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 5504#define mmSPI_PERFCOUNTER5_HI 0x318a 5505#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 5506#define mmSPI_PERFCOUNTER5_LO 0x318b 5507#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 5508#define mmSQ_PERFCOUNTER0_LO 0x31c0 5509#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 5510#define mmSQ_PERFCOUNTER0_HI 0x31c1 5511#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 5512#define mmSQ_PERFCOUNTER1_LO 0x31c2 5513#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 5514#define mmSQ_PERFCOUNTER1_HI 0x31c3 5515#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 5516#define mmSQ_PERFCOUNTER2_LO 0x31c4 5517#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 5518#define mmSQ_PERFCOUNTER2_HI 0x31c5 5519#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 5520#define mmSQ_PERFCOUNTER3_LO 0x31c6 5521#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 5522#define mmSQ_PERFCOUNTER3_HI 0x31c7 5523#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 5524#define mmSQ_PERFCOUNTER4_LO 0x31c8 5525#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 5526#define mmSQ_PERFCOUNTER4_HI 0x31c9 5527#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 5528#define mmSQ_PERFCOUNTER5_LO 0x31ca 5529#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 5530#define mmSQ_PERFCOUNTER5_HI 0x31cb 5531#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 5532#define mmSQ_PERFCOUNTER6_LO 0x31cc 5533#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 5534#define mmSQ_PERFCOUNTER6_HI 0x31cd 5535#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 5536#define mmSQ_PERFCOUNTER7_LO 0x31ce 5537#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 5538#define mmSQ_PERFCOUNTER7_HI 0x31cf 5539#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 5540#define mmSQ_PERFCOUNTER8_LO 0x31d0 5541#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 5542#define mmSQ_PERFCOUNTER8_HI 0x31d1 5543#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 5544#define mmSQ_PERFCOUNTER9_LO 0x31d2 5545#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 5546#define mmSQ_PERFCOUNTER9_HI 0x31d3 5547#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 5548#define mmSQ_PERFCOUNTER10_LO 0x31d4 5549#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 5550#define mmSQ_PERFCOUNTER10_HI 0x31d5 5551#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 5552#define mmSQ_PERFCOUNTER11_LO 0x31d6 5553#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 5554#define mmSQ_PERFCOUNTER11_HI 0x31d7 5555#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 5556#define mmSQ_PERFCOUNTER12_LO 0x31d8 5557#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 5558#define mmSQ_PERFCOUNTER12_HI 0x31d9 5559#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 5560#define mmSQ_PERFCOUNTER13_LO 0x31da 5561#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 5562#define mmSQ_PERFCOUNTER13_HI 0x31db 5563#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 5564#define mmSQ_PERFCOUNTER14_LO 0x31dc 5565#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 5566#define mmSQ_PERFCOUNTER14_HI 0x31dd 5567#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 5568#define mmSQ_PERFCOUNTER15_LO 0x31de 5569#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 5570#define mmSQ_PERFCOUNTER15_HI 0x31df 5571#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 5572#define mmSX_PERFCOUNTER0_LO 0x3240 5573#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 5574#define mmSX_PERFCOUNTER0_HI 0x3241 5575#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 5576#define mmSX_PERFCOUNTER1_LO 0x3242 5577#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 5578#define mmSX_PERFCOUNTER1_HI 0x3243 5579#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 5580#define mmSX_PERFCOUNTER2_LO 0x3244 5581#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 5582#define mmSX_PERFCOUNTER2_HI 0x3245 5583#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 5584#define mmSX_PERFCOUNTER3_LO 0x3246 5585#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 5586#define mmSX_PERFCOUNTER3_HI 0x3247 5587#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 5588#define mmGDS_PERFCOUNTER0_LO 0x3280 5589#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 5590#define mmGDS_PERFCOUNTER0_HI 0x3281 5591#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 5592#define mmGDS_PERFCOUNTER1_LO 0x3282 5593#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 5594#define mmGDS_PERFCOUNTER1_HI 0x3283 5595#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 5596#define mmGDS_PERFCOUNTER2_LO 0x3284 5597#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 5598#define mmGDS_PERFCOUNTER2_HI 0x3285 5599#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 5600#define mmGDS_PERFCOUNTER3_LO 0x3286 5601#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 5602#define mmGDS_PERFCOUNTER3_HI 0x3287 5603#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 5604#define mmTA_PERFCOUNTER0_LO 0x32c0 5605#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 5606#define mmTA_PERFCOUNTER0_HI 0x32c1 5607#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 5608#define mmTA_PERFCOUNTER1_LO 0x32c2 5609#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 5610#define mmTA_PERFCOUNTER1_HI 0x32c3 5611#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 5612#define mmTD_PERFCOUNTER0_LO 0x3300 5613#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 5614#define mmTD_PERFCOUNTER0_HI 0x3301 5615#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 5616#define mmTD_PERFCOUNTER1_LO 0x3302 5617#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 5618#define mmTD_PERFCOUNTER1_HI 0x3303 5619#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 5620#define mmTCP_PERFCOUNTER0_LO 0x3340 5621#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 5622#define mmTCP_PERFCOUNTER0_HI 0x3341 5623#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 5624#define mmTCP_PERFCOUNTER1_LO 0x3342 5625#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 5626#define mmTCP_PERFCOUNTER1_HI 0x3343 5627#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 5628#define mmTCP_PERFCOUNTER2_LO 0x3344 5629#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 5630#define mmTCP_PERFCOUNTER2_HI 0x3345 5631#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 5632#define mmTCP_PERFCOUNTER3_LO 0x3346 5633#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 5634#define mmTCP_PERFCOUNTER3_HI 0x3347 5635#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 5636#define mmTCC_PERFCOUNTER0_LO 0x3380 5637#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1 5638#define mmTCC_PERFCOUNTER0_HI 0x3381 5639#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1 5640#define mmTCC_PERFCOUNTER1_LO 0x3382 5641#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1 5642#define mmTCC_PERFCOUNTER1_HI 0x3383 5643#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1 5644#define mmTCC_PERFCOUNTER2_LO 0x3384 5645#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1 5646#define mmTCC_PERFCOUNTER2_HI 0x3385 5647#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1 5648#define mmTCC_PERFCOUNTER3_LO 0x3386 5649#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1 5650#define mmTCC_PERFCOUNTER3_HI 0x3387 5651#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1 5652#define mmTCA_PERFCOUNTER0_LO 0x3390 5653#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1 5654#define mmTCA_PERFCOUNTER0_HI 0x3391 5655#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1 5656#define mmTCA_PERFCOUNTER1_LO 0x3392 5657#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1 5658#define mmTCA_PERFCOUNTER1_HI 0x3393 5659#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1 5660#define mmTCA_PERFCOUNTER2_LO 0x3394 5661#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1 5662#define mmTCA_PERFCOUNTER2_HI 0x3395 5663#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1 5664#define mmTCA_PERFCOUNTER3_LO 0x3396 5665#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1 5666#define mmTCA_PERFCOUNTER3_HI 0x3397 5667#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1 5668#define mmCB_PERFCOUNTER0_LO 0x3406 5669#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 5670#define mmCB_PERFCOUNTER0_HI 0x3407 5671#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 5672#define mmCB_PERFCOUNTER1_LO 0x3408 5673#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 5674#define mmCB_PERFCOUNTER1_HI 0x3409 5675#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 5676#define mmCB_PERFCOUNTER2_LO 0x340a 5677#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 5678#define mmCB_PERFCOUNTER2_HI 0x340b 5679#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 5680#define mmCB_PERFCOUNTER3_LO 0x340c 5681#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 5682#define mmCB_PERFCOUNTER3_HI 0x340d 5683#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 5684#define mmDB_PERFCOUNTER0_LO 0x3440 5685#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 5686#define mmDB_PERFCOUNTER0_HI 0x3441 5687#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 5688#define mmDB_PERFCOUNTER1_LO 0x3442 5689#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 5690#define mmDB_PERFCOUNTER1_HI 0x3443 5691#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 5692#define mmDB_PERFCOUNTER2_LO 0x3444 5693#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 5694#define mmDB_PERFCOUNTER2_HI 0x3445 5695#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 5696#define mmDB_PERFCOUNTER3_LO 0x3446 5697#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 5698#define mmDB_PERFCOUNTER3_HI 0x3447 5699#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 5700#define mmRLC_PERFCOUNTER0_LO 0x3480 5701#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 5702#define mmRLC_PERFCOUNTER0_HI 0x3481 5703#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 5704#define mmRLC_PERFCOUNTER1_LO 0x3482 5705#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 5706#define mmRLC_PERFCOUNTER1_HI 0x3483 5707#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 5708#define mmRMI_PERFCOUNTER0_LO 0x34c0 5709#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 5710#define mmRMI_PERFCOUNTER0_HI 0x34c1 5711#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 5712#define mmRMI_PERFCOUNTER1_LO 0x34c2 5713#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 5714#define mmRMI_PERFCOUNTER1_HI 0x34c3 5715#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 5716#define mmRMI_PERFCOUNTER2_LO 0x34c4 5717#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 5718#define mmRMI_PERFCOUNTER2_HI 0x34c5 5719#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 5720#define mmRMI_PERFCOUNTER3_LO 0x34c6 5721#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 5722#define mmRMI_PERFCOUNTER3_HI 0x34c7 5723#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 5724 5725 5726// addressBlock: gc_utcl2_atcl2pfcntrdec 5727// base address: 0x35400 5728#define mmATC_L2_PERFCOUNTER_LO 0x3500 5729#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1 5730#define mmATC_L2_PERFCOUNTER_HI 0x3501 5731#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1 5732 5733 5734// addressBlock: gc_utcl2_vml2prdec 5735// base address: 0x35420 5736#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508 5737#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 5738#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509 5739#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 5740 5741 5742// addressBlock: gc_perfsdec 5743// base address: 0x36000 5744#define mmCPG_PERFCOUNTER1_SELECT 0x3800 5745#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 5746#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 5747#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 5748#define mmCPG_PERFCOUNTER0_SELECT 0x3802 5749#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 5750#define mmCPC_PERFCOUNTER1_SELECT 0x3803 5751#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 5752#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 5753#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5754#define mmCPF_PERFCOUNTER1_SELECT 0x3805 5755#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 5756#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 5757#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 5758#define mmCPF_PERFCOUNTER0_SELECT 0x3807 5759#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 5760#define mmCP_PERFMON_CNTL 0x3808 5761#define mmCP_PERFMON_CNTL_BASE_IDX 1 5762#define mmCPC_PERFCOUNTER0_SELECT 0x3809 5763#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 5764#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 5765#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5766#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 5767#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5768#define mmCPF_LATENCY_STATS_SELECT 0x380c 5769#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 5770#define mmCPG_LATENCY_STATS_SELECT 0x380d 5771#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 5772#define mmCPC_LATENCY_STATS_SELECT 0x380e 5773#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 5774#define mmCP_DRAW_OBJECT 0x3810 5775#define mmCP_DRAW_OBJECT_BASE_IDX 1 5776#define mmCP_DRAW_OBJECT_COUNTER 0x3811 5777#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 5778#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 5779#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 5780#define mmCP_DRAW_WINDOW_HI 0x3813 5781#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 5782#define mmCP_DRAW_WINDOW_LO 0x3814 5783#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 5784#define mmCP_DRAW_WINDOW_CNTL 0x3815 5785#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 5786#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 5787#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 5788#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 5789#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 5790#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 5791#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 5792#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 5793#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 5794#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 5795#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 5796#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 5797#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 5798#define mmWD_PERFCOUNTER0_SELECT 0x3880 5799#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1 5800#define mmWD_PERFCOUNTER1_SELECT 0x3881 5801#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1 5802#define mmWD_PERFCOUNTER2_SELECT 0x3882 5803#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1 5804#define mmWD_PERFCOUNTER3_SELECT 0x3883 5805#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1 5806#define mmIA_PERFCOUNTER0_SELECT 0x3884 5807#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1 5808#define mmIA_PERFCOUNTER1_SELECT 0x3885 5809#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1 5810#define mmIA_PERFCOUNTER2_SELECT 0x3886 5811#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1 5812#define mmIA_PERFCOUNTER3_SELECT 0x3887 5813#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1 5814#define mmIA_PERFCOUNTER0_SELECT1 0x3888 5815#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5816#define mmVGT_PERFCOUNTER0_SELECT 0x388c 5817#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 5818#define mmVGT_PERFCOUNTER1_SELECT 0x388d 5819#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 5820#define mmVGT_PERFCOUNTER2_SELECT 0x388e 5821#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 5822#define mmVGT_PERFCOUNTER3_SELECT 0x388f 5823#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 5824#define mmVGT_PERFCOUNTER0_SELECT1 0x3890 5825#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 5826#define mmVGT_PERFCOUNTER1_SELECT1 0x3891 5827#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 5828#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894 5829#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 5830#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 5831#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 5832#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 5833#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 5834#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 5835#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 5836#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 5837#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 5838#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 5839#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 5840#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905 5841#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 5842#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 5843#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 5844#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 5845#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5846#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 5847#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 5848#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 5849#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 5850#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 5851#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 5852#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 5853#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 5854#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 5855#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 5856#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 5857#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 5858#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 5859#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 5860#define mmSPI_PERFCOUNTER0_SELECT 0x3980 5861#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 5862#define mmSPI_PERFCOUNTER1_SELECT 0x3981 5863#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 5864#define mmSPI_PERFCOUNTER2_SELECT 0x3982 5865#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 5866#define mmSPI_PERFCOUNTER3_SELECT 0x3983 5867#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 5868#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 5869#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 5870#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 5871#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 5872#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 5873#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 5874#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 5875#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 5876#define mmSPI_PERFCOUNTER4_SELECT 0x3988 5877#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 5878#define mmSPI_PERFCOUNTER5_SELECT 0x3989 5879#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 5880#define mmSPI_PERFCOUNTER_BINS 0x398a 5881#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 5882#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 5883#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 5884#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 5885#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 5886#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 5887#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 5888#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 5889#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 5890#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 5891#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 5892#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 5893#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 5894#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 5895#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 5896#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 5897#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 5898#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 5899#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 5900#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 5901#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 5902#define mmSQ_PERFCOUNTER10_SELECT 0x39ca 5903#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 5904#define mmSQ_PERFCOUNTER11_SELECT 0x39cb 5905#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 5906#define mmSQ_PERFCOUNTER12_SELECT 0x39cc 5907#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 5908#define mmSQ_PERFCOUNTER13_SELECT 0x39cd 5909#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 5910#define mmSQ_PERFCOUNTER14_SELECT 0x39ce 5911#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 5912#define mmSQ_PERFCOUNTER15_SELECT 0x39cf 5913#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 5914#define mmSQ_PERFCOUNTER_CTRL 0x39e0 5915#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 5916#define mmSQ_PERFCOUNTER_MASK 0x39e1 5917#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1 5918#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 5919#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 5920#define mmSX_PERFCOUNTER0_SELECT 0x3a40 5921#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 5922#define mmSX_PERFCOUNTER1_SELECT 0x3a41 5923#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 5924#define mmSX_PERFCOUNTER2_SELECT 0x3a42 5925#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 5926#define mmSX_PERFCOUNTER3_SELECT 0x3a43 5927#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 5928#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 5929#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 5930#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 5931#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 5932#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 5933#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 5934#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 5935#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 5936#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 5937#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 5938#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 5939#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 5940#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 5941#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 5942#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 5943#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 5944#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 5945#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5946#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 5947#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 5948#define mmTD_PERFCOUNTER0_SELECT 0x3b00 5949#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 5950#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 5951#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 5952#define mmTD_PERFCOUNTER1_SELECT 0x3b02 5953#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 5954#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 5955#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 5956#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 5957#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 5958#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 5959#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 5960#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 5961#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 5962#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 5963#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 5964#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 5965#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 5966#define mmTCC_PERFCOUNTER0_SELECT 0x3b80 5967#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 5968#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81 5969#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5970#define mmTCC_PERFCOUNTER1_SELECT 0x3b82 5971#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 5972#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83 5973#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 5974#define mmTCC_PERFCOUNTER2_SELECT 0x3b84 5975#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 5976#define mmTCC_PERFCOUNTER3_SELECT 0x3b85 5977#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 5978#define mmTCA_PERFCOUNTER0_SELECT 0x3b90 5979#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 5980#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91 5981#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5982#define mmTCA_PERFCOUNTER1_SELECT 0x3b92 5983#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 5984#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93 5985#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 5986#define mmTCA_PERFCOUNTER2_SELECT 0x3b94 5987#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 5988#define mmTCA_PERFCOUNTER3_SELECT 0x3b95 5989#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 5990#define mmCB_PERFCOUNTER_FILTER 0x3c00 5991#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 5992#define mmCB_PERFCOUNTER0_SELECT 0x3c01 5993#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 5994#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 5995#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 5996#define mmCB_PERFCOUNTER1_SELECT 0x3c03 5997#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 5998#define mmCB_PERFCOUNTER2_SELECT 0x3c04 5999#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 6000#define mmCB_PERFCOUNTER3_SELECT 0x3c05 6001#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 6002#define mmDB_PERFCOUNTER0_SELECT 0x3c40 6003#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 6004#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 6005#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 6006#define mmDB_PERFCOUNTER1_SELECT 0x3c42 6007#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 6008#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 6009#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 6010#define mmDB_PERFCOUNTER2_SELECT 0x3c44 6011#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 6012#define mmDB_PERFCOUNTER3_SELECT 0x3c46 6013#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 6014#define mmRLC_SPM_PERFMON_CNTL 0x3c80 6015#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 6016#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 6017#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 6018#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 6019#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 6020#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 6021#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 6022#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 6023#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 6024#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85 6025#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 6026#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86 6027#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 6028#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 6029#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6030#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 6031#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6032#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 6033#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6034#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a 6035#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6036#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b 6037#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6038#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c 6039#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6040#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d 6041#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6042#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e 6043#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6044#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 6045#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6046#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 6047#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6048#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 6049#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6050#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 6051#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6052#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 6053#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6054#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 6055#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6056#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 6057#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6058#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 6059#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6060#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 6061#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6062#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a 6063#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6064#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b 6065#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 6066#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c 6067#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 6068#define mmRLC_SPM_RING_RDPTR 0x3c9d 6069#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 6070#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e 6071#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 6072#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 6073#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6074#define mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 6075#define mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 6076#define mmRLC_PERFMON_CLK_CNTL_UCODE 0x3cbe 6077#define mmRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 6078#define mmRLC_PERFMON_CLK_CNTL 0x3cbf 6079#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 6080#define mmRLC_PERFMON_CNTL 0x3cc0 6081#define mmRLC_PERFMON_CNTL_BASE_IDX 1 6082#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 6083#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 6084#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 6085#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 6086#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 6087#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 6088#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 6089#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 6090#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 6091#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 6092#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 6093#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 6094#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 6095#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 6096#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 6097#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 6098#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 6099#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 6100#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 6101#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 6102#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 6103#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 6104#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 6105#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 6106#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 6107#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 6108#define mmRMI_PERF_COUNTER_CNTL 0x3d06 6109#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 6110 6111 6112// addressBlock: gc_utcl2_atcl2pfcntldec 6113// base address: 0x37500 6114#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40 6115#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6116#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41 6117#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6118#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 6119#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6120 6121 6122// addressBlock: gc_utcl2_vml2pldec 6123// base address: 0x37530 6124#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c 6125#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6126#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d 6127#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6128#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e 6129#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 6130#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f 6131#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 6132#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 6133#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 6134#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 6135#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 6136#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 6137#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 6138#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 6139#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 6140#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 6141#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6142 6143 6144// addressBlock: gc_rlcpdec 6145// base address: 0x3b000 6146#define mmRLC_CNTL 0x4c00 6147#define mmRLC_CNTL_BASE_IDX 1 6148#define mmRLC_STAT 0x4c04 6149#define mmRLC_STAT_BASE_IDX 1 6150#define mmRLC_SAFE_MODE 0x4c05 6151#define mmRLC_SAFE_MODE_BASE_IDX 1 6152#define mmRLC_MEM_SLP_CNTL 0x4c06 6153#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 6154#define mmSMU_RLC_RESPONSE 0x4c07 6155#define mmSMU_RLC_RESPONSE_BASE_IDX 1 6156#define mmRLC_RLCV_SAFE_MODE 0x4c08 6157#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 6158#define mmRLC_SMU_SAFE_MODE 0x4c09 6159#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 6160#define mmRLC_RLCV_COMMAND 0x4c0a 6161#define mmRLC_RLCV_COMMAND_BASE_IDX 1 6162#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 6163#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 6164#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 6165#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 6166#define mmRLC_GPM_TIMER_INT_0 0x4c0e 6167#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 6168#define mmRLC_GPM_TIMER_INT_1 0x4c0f 6169#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 6170#define mmRLC_GPM_TIMER_INT_2 0x4c10 6171#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 6172#define mmRLC_GPM_TIMER_CTRL 0x4c11 6173#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 6174#define mmRLC_LB_CNTR_MAX 0x4c12 6175#define mmRLC_LB_CNTR_MAX_BASE_IDX 1 6176#define mmRLC_GPM_TIMER_STAT 0x4c13 6177#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 6178#define mmRLC_GPM_TIMER_INT_3 0x4c15 6179#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 6180#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 6181#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 6182#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 6183#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 6184#define mmRLC_INT_STAT 0x4c18 6185#define mmRLC_INT_STAT_BASE_IDX 1 6186#define mmRLC_LB_CNTL 0x4c19 6187#define mmRLC_LB_CNTL_BASE_IDX 1 6188#define mmRLC_MGCG_CTRL 0x4c1a 6189#define mmRLC_MGCG_CTRL_BASE_IDX 1 6190#define mmRLC_LB_CNTR_INIT 0x4c1b 6191#define mmRLC_LB_CNTR_INIT_BASE_IDX 1 6192#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c 6193#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 6194#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e 6195#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 6196#define mmRLC_PG_DELAY_2 0x4c1f 6197#define mmRLC_PG_DELAY_2_BASE_IDX 1 6198#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 6199#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 6200#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 6201#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 6202#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 6203#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 6204#define mmRLC_UCODE_CNTL 0x4c27 6205#define mmRLC_UCODE_CNTL_BASE_IDX 1 6206#define mmRLC_GPM_THREAD_RESET 0x4c28 6207#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 6208#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 6209#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 6210#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 6211#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 6212#define mmRLC_FIREWALL_VIOLATION 0x4c2b 6213#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1 6214#define mmRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 6215#define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 6216#define mmRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 6217#define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 6218#define mmRLC_CLK_COUNT_REFCLK_LSB 0x4c32 6219#define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 6220#define mmRLC_CLK_COUNT_REFCLK_MSB 0x4c33 6221#define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 6222#define mmRLC_CLK_COUNT_CTRL 0x4c34 6223#define mmRLC_CLK_COUNT_CTRL_BASE_IDX 1 6224#define mmRLC_CLK_COUNT_STAT 0x4c35 6225#define mmRLC_CLK_COUNT_STAT_BASE_IDX 1 6226#define mmRLC_GPM_STAT 0x4c40 6227#define mmRLC_GPM_STAT_BASE_IDX 1 6228#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 6229#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 6230#define mmRLC_GPU_CLOCK_32 0x4c42 6231#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 6232#define mmRLC_PG_CNTL 0x4c43 6233#define mmRLC_PG_CNTL_BASE_IDX 1 6234#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 6235#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 6236#define mmRLC_GPM_THREAD_ENABLE 0x4c45 6237#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 6238#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 6239#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 6240#define mmRLC_CGCG_CGLS_CTRL 0x4c49 6241#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 6242#define mmRLC_CGCG_RAMP_CTRL 0x4c4a 6243#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 6244#define mmRLC_DYN_PG_STATUS 0x4c4b 6245#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 6246#define mmRLC_DYN_PG_REQUEST 0x4c4c 6247#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 6248#define mmRLC_PG_DELAY 0x4c4d 6249#define mmRLC_PG_DELAY_BASE_IDX 1 6250#define mmRLC_CU_STATUS 0x4c4e 6251#define mmRLC_CU_STATUS_BASE_IDX 1 6252#define mmRLC_LB_INIT_CU_MASK 0x4c4f 6253#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1 6254#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 6255#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 6256#define mmRLC_LB_PARAMS 0x4c51 6257#define mmRLC_LB_PARAMS_BASE_IDX 1 6258#define mmRLC_THREAD1_DELAY 0x4c52 6259#define mmRLC_THREAD1_DELAY_BASE_IDX 1 6260#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 6261#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 6262#define mmRLC_MAX_PG_CU 0x4c54 6263#define mmRLC_MAX_PG_CU_BASE_IDX 1 6264#define mmRLC_AUTO_PG_CTRL 0x4c55 6265#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 6266#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 6267#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 6268#define mmRLC_SERDES_RD_PENDING 0x4c58 6269#define mmRLC_SERDES_RD_PENDING_BASE_IDX 1 6270#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59 6271#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 6272#define mmRLC_SERDES_RD_DATA_0 0x4c5a 6273#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 6274#define mmRLC_SERDES_RD_DATA_1 0x4c5b 6275#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 6276#define mmRLC_SERDES_RD_DATA_2 0x4c5c 6277#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 6278#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d 6279#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 6280#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e 6281#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 6282#define mmRLC_SERDES_WR_CTRL 0x4c5f 6283#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1 6284#define mmRLC_SERDES_WR_DATA 0x4c60 6285#define mmRLC_SERDES_WR_DATA_BASE_IDX 1 6286#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61 6287#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 6288#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 6289#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 6290#define mmRLC_GPM_GENERAL_0 0x4c63 6291#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 6292#define mmRLC_GPM_GENERAL_1 0x4c64 6293#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 6294#define mmRLC_GPM_GENERAL_2 0x4c65 6295#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 6296#define mmRLC_GPM_GENERAL_3 0x4c66 6297#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 6298#define mmRLC_GPM_GENERAL_4 0x4c67 6299#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 6300#define mmRLC_GPM_GENERAL_5 0x4c68 6301#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 6302#define mmRLC_GPM_GENERAL_6 0x4c69 6303#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 6304#define mmRLC_GPM_GENERAL_7 0x4c6a 6305#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 6306#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c 6307#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 6308#define mmRLC_GPM_SCRATCH_DATA 0x4c6d 6309#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 6310#define mmRLC_STATIC_PG_STATUS 0x4c6e 6311#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 6312#define mmRLC_SPM_MC_CNTL 0x4c71 6313#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 6314#define mmRLC_SPM_INT_CNTL 0x4c72 6315#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 6316#define mmRLC_SPM_INT_STATUS 0x4c73 6317#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 6318#define mmRLC_SMU_MESSAGE 0x4c76 6319#define mmRLC_SMU_MESSAGE_BASE_IDX 1 6320#define mmRLC_GPM_LOG_SIZE 0x4c77 6321#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 6322#define mmRLC_PG_DELAY_3 0x4c78 6323#define mmRLC_PG_DELAY_3_BASE_IDX 1 6324#define mmRLC_GPR_REG1 0x4c79 6325#define mmRLC_GPR_REG1_BASE_IDX 1 6326#define mmRLC_GPR_REG2 0x4c7a 6327#define mmRLC_GPR_REG2_BASE_IDX 1 6328#define mmRLC_GPM_LOG_CONT 0x4c7b 6329#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 6330#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c 6331#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 6332#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e 6333#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 6334#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f 6335#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 6336#define mmRLC_SRM_CNTL 0x4c80 6337#define mmRLC_SRM_CNTL_BASE_IDX 1 6338#define mmRLC_SRM_ARAM_ADDR 0x4c83 6339#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 6340#define mmRLC_SRM_ARAM_DATA 0x4c84 6341#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 6342#define mmRLC_SRM_DRAM_ADDR 0x4c85 6343#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 6344#define mmRLC_SRM_DRAM_DATA 0x4c86 6345#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 6346#define mmRLC_SRM_GPM_COMMAND 0x4c87 6347#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 6348#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 6349#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 6350#define mmRLC_SRM_RLCV_COMMAND 0x4c89 6351#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 6352#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a 6353#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 6354#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 6355#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 6356#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 6357#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 6358#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 6359#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 6360#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 6361#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 6362#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 6363#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 6364#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 6365#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 6366#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 6367#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 6368#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 6369#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 6370#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 6371#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 6372#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 6373#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 6374#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 6375#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 6376#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 6377#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 6378#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 6379#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 6380#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 6381#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 6382#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 6383#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 6384#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 6385#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 6386#define mmRLC_SRM_STAT 0x4c9b 6387#define mmRLC_SRM_STAT_BASE_IDX 1 6388#define mmRLC_SRM_GPM_ABORT 0x4c9c 6389#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 6390#define mmRLC_CSIB_ADDR_LO 0x4ca2 6391#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 6392#define mmRLC_CSIB_ADDR_HI 0x4ca3 6393#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 6394#define mmRLC_CSIB_LENGTH 0x4ca4 6395#define mmRLC_CSIB_LENGTH_BASE_IDX 1 6396#define mmRLC_SMU_COMMAND 0x4ca9 6397#define mmRLC_SMU_COMMAND_BASE_IDX 1 6398#define mmRLC_CP_SCHEDULERS 0x4caa 6399#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 6400#define mmRLC_SMU_ARGUMENT_1 0x4cab 6401#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 6402#define mmRLC_SMU_ARGUMENT_2 0x4cac 6403#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 6404#define mmRLC_GPM_GENERAL_8 0x4cad 6405#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 6406#define mmRLC_GPM_GENERAL_9 0x4cae 6407#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 6408#define mmRLC_GPM_GENERAL_10 0x4caf 6409#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 6410#define mmRLC_GPM_GENERAL_11 0x4cb0 6411#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 6412#define mmRLC_GPM_GENERAL_12 0x4cb1 6413#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 6414#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 6415#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 6416#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 6417#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 6418#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 6419#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 6420#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 6421#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 6422#define mmRLC_UTCL1_STATUS_2 0x4cb6 6423#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 6424#define mmRLC_LB_THR_CONFIG_2 0x4cb8 6425#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1 6426#define mmRLC_LB_THR_CONFIG_3 0x4cb9 6427#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1 6428#define mmRLC_LB_THR_CONFIG_4 0x4cba 6429#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1 6430#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc 6431#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 6432#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd 6433#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 6434#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 6435#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 6436#define mmRLC_LB_THR_CONFIG_1 0x4cbf 6437#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1 6438#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 6439#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 6440#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 6441#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 6442#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 6443#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 6444#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 6445#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 6446#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 6447#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 6448#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 6449#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 6450#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 6451#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 6452#define mmRLC_SEMAPHORE_0 0x4cc7 6453#define mmRLC_SEMAPHORE_0_BASE_IDX 1 6454#define mmRLC_SEMAPHORE_1 0x4cc8 6455#define mmRLC_SEMAPHORE_1_BASE_IDX 1 6456#define mmRLC_CP_EOF_INT 0x4cca 6457#define mmRLC_CP_EOF_INT_BASE_IDX 1 6458#define mmRLC_CP_EOF_INT_CNT 0x4ccb 6459#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 6460#define mmRLC_SPARE_INT 0x4ccc 6461#define mmRLC_SPARE_INT_BASE_IDX 1 6462#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd 6463#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 6464#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce 6465#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 6466#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf 6467#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 6468#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 6469#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 6470#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 6471#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 6472#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 6473#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 6474#define mmRLC_DSM_TRIG 0x4cd3 6475#define mmRLC_DSM_TRIG_BASE_IDX 1 6476#define mmRLC_UTCL1_STATUS 0x4cd4 6477#define mmRLC_UTCL1_STATUS_BASE_IDX 1 6478#define mmRLC_R2I_CNTL_0 0x4cd5 6479#define mmRLC_R2I_CNTL_0_BASE_IDX 1 6480#define mmRLC_R2I_CNTL_1 0x4cd6 6481#define mmRLC_R2I_CNTL_1_BASE_IDX 1 6482#define mmRLC_R2I_CNTL_2 0x4cd7 6483#define mmRLC_R2I_CNTL_2_BASE_IDX 1 6484#define mmRLC_R2I_CNTL_3 0x4cd8 6485#define mmRLC_R2I_CNTL_3_BASE_IDX 1 6486#define mmRLC_UTCL2_CNTL 0x4cd9 6487#define mmRLC_UTCL2_CNTL_BASE_IDX 1 6488#define mmRLC_LBPW_CU_STAT 0x4cda 6489#define mmRLC_LBPW_CU_STAT_BASE_IDX 1 6490#define mmRLC_DS_CNTL 0x4cdb 6491#define mmRLC_DS_CNTL_BASE_IDX 1 6492#define mmRLC_GPM_INT_STAT_TH0 0x4cdc 6493#define mmRLC_GPM_INT_STAT_TH0_BASE_IDX 1 6494#define mmRLC_GPM_GENERAL_13 0x4cdd 6495#define mmRLC_GPM_GENERAL_13_BASE_IDX 1 6496#define mmRLC_GPM_GENERAL_14 0x4cde 6497#define mmRLC_GPM_GENERAL_14_BASE_IDX 1 6498#define mmRLC_GPM_GENERAL_15 0x4cdf 6499#define mmRLC_GPM_GENERAL_15_BASE_IDX 1 6500#define mmRLC_SPARE_INT_1 0x4ce0 6501#define mmRLC_SPARE_INT_1_BASE_IDX 1 6502#define mmRLC_RLCV_SPARE_INT_1 0x4ce1 6503#define mmRLC_RLCV_SPARE_INT_1_BASE_IDX 1 6504#define mmRLC_SEMAPHORE_2 0x4ce3 6505#define mmRLC_SEMAPHORE_2_BASE_IDX 1 6506#define mmRLC_SEMAPHORE_3 0x4ce4 6507#define mmRLC_SEMAPHORE_3_BASE_IDX 1 6508#define mmRLC_SMU_ARGUMENT_3 0x4ce5 6509#define mmRLC_SMU_ARGUMENT_3_BASE_IDX 1 6510#define mmRLC_SMU_ARGUMENT_4 0x4ce6 6511#define mmRLC_SMU_ARGUMENT_4_BASE_IDX 1 6512#define mmRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 6513#define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 6514#define mmRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 6515#define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 6516#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea 6517#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 6518#define mmRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb 6519#define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 6520#define mmRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec 6521#define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 6522#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef 6523#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 6524#define mmRLC_CPG_STAT_INVAL 0x4d09 6525#define mmRLC_CPG_STAT_INVAL_BASE_IDX 1 6526#define mmRLC_RLCV_SPARE_INT 0x4f30 6527#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 6528#define mmRLC_SMU_CLK_REQ 0x4f97 6529#define mmRLC_SMU_CLK_REQ_BASE_IDX 1 6530 6531 6532// addressBlock: gc_pwrdec 6533// base address: 0x3c000 6534#define mmCGTS_SM_CTRL_REG 0x5000 6535#define mmCGTS_SM_CTRL_REG_BASE_IDX 1 6536#define mmCGTS_RD_CTRL_REG 0x5001 6537#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 6538#define mmCGTS_RD_REG 0x5002 6539#define mmCGTS_RD_REG_BASE_IDX 1 6540#define mmCGTS_TCC_DISABLE 0x5003 6541#define mmCGTS_TCC_DISABLE_BASE_IDX 1 6542#define mmCGTS_USER_TCC_DISABLE 0x5004 6543#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 6544#define mmCGTS_CU0_SP0_CTRL_REG 0x5008 6545#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 6546#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 6547#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 6548#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a 6549#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 6550#define mmCGTS_CU0_SP1_CTRL_REG 0x500b 6551#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 6552#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c 6553#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 6554#define mmCGTS_CU1_SP0_CTRL_REG 0x500d 6555#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 6556#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e 6557#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 6558#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f 6559#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 6560#define mmCGTS_CU1_SP1_CTRL_REG 0x5010 6561#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 6562#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011 6563#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 6564#define mmCGTS_CU2_SP0_CTRL_REG 0x5012 6565#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 6566#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 6567#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 6568#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014 6569#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 6570#define mmCGTS_CU2_SP1_CTRL_REG 0x5015 6571#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 6572#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016 6573#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 6574#define mmCGTS_CU3_SP0_CTRL_REG 0x5017 6575#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 6576#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 6577#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 6578#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019 6579#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 6580#define mmCGTS_CU3_SP1_CTRL_REG 0x501a 6581#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 6582#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b 6583#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 6584#define mmCGTS_CU4_SP0_CTRL_REG 0x501c 6585#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 6586#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d 6587#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 6588#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e 6589#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 6590#define mmCGTS_CU4_SP1_CTRL_REG 0x501f 6591#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 6592#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020 6593#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 6594#define mmCGTS_CU5_SP0_CTRL_REG 0x5021 6595#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 6596#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 6597#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 6598#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023 6599#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 6600#define mmCGTS_CU5_SP1_CTRL_REG 0x5024 6601#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 6602#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025 6603#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 6604#define mmCGTS_CU6_SP0_CTRL_REG 0x5026 6605#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 6606#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 6607#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 6608#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028 6609#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 6610#define mmCGTS_CU6_SP1_CTRL_REG 0x5029 6611#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 6612#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a 6613#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 6614#define mmCGTS_CU7_SP0_CTRL_REG 0x502b 6615#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 6616#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c 6617#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 6618#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d 6619#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 6620#define mmCGTS_CU7_SP1_CTRL_REG 0x502e 6621#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 6622#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f 6623#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 6624#define mmCGTS_CU8_SP0_CTRL_REG 0x5030 6625#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 6626#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 6627#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 6628#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032 6629#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 6630#define mmCGTS_CU8_SP1_CTRL_REG 0x5033 6631#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 6632#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034 6633#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 6634#define mmCGTS_CU9_SP0_CTRL_REG 0x5035 6635#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 6636#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 6637#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 6638#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037 6639#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 6640#define mmCGTS_CU9_SP1_CTRL_REG 0x5038 6641#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 6642#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039 6643#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 6644#define mmCGTS_CU10_SP0_CTRL_REG 0x503a 6645#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 6646#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b 6647#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 6648#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c 6649#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 6650#define mmCGTS_CU10_SP1_CTRL_REG 0x503d 6651#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 6652#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e 6653#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 6654#define mmCGTS_CU11_SP0_CTRL_REG 0x503f 6655#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 6656#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 6657#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 6658#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041 6659#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 6660#define mmCGTS_CU11_SP1_CTRL_REG 0x5042 6661#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 6662#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043 6663#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 6664#define mmCGTS_CU12_SP0_CTRL_REG 0x5044 6665#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 6666#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 6667#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 6668#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046 6669#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 6670#define mmCGTS_CU12_SP1_CTRL_REG 0x5047 6671#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 6672#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048 6673#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 6674#define mmCGTS_CU13_SP0_CTRL_REG 0x5049 6675#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 6676#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a 6677#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 6678#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b 6679#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 6680#define mmCGTS_CU13_SP1_CTRL_REG 0x504c 6681#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 6682#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d 6683#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 6684#define mmCGTS_CU14_SP0_CTRL_REG 0x504e 6685#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 6686#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f 6687#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 6688#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050 6689#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 6690#define mmCGTS_CU14_SP1_CTRL_REG 0x5051 6691#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 6692#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052 6693#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 6694#define mmCGTS_CU15_SP0_CTRL_REG 0x5053 6695#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 6696#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 6697#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 6698#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055 6699#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 6700#define mmCGTS_CU15_SP1_CTRL_REG 0x5056 6701#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 6702#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057 6703#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 6704#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058 6705#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 6706#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059 6707#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 6708#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a 6709#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 6710#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b 6711#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 6712#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c 6713#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 6714#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d 6715#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 6716#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e 6717#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 6718#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f 6719#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 6720#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060 6721#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 6722#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061 6723#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 6724#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062 6725#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 6726#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063 6727#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 6728#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064 6729#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 6730#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065 6731#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 6732#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066 6733#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 6734#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067 6735#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 6736#define mmCGTT_SPI_PS_CLK_CTRL 0x507d 6737#define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 6738#define mmCGTT_SPIS_CLK_CTRL 0x507e 6739#define mmCGTT_SPIS_CLK_CTRL_BASE_IDX 1 6740#define mmCGTX_SPI_DEBUG_CLK_CTRL 0x507f 6741#define mmCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 6742#define mmCGTT_SPI_CLK_CTRL 0x5080 6743#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 6744#define mmCGTT_PC_CLK_CTRL 0x5081 6745#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 6746#define mmCGTT_BCI_CLK_CTRL 0x5082 6747#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 6748#define mmCGTT_VGT_CLK_CTRL 0x5084 6749#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 6750#define mmCGTT_IA_CLK_CTRL 0x5085 6751#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 6752#define mmCGTT_WD_CLK_CTRL 0x5086 6753#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 6754#define mmCGTT_PA_CLK_CTRL 0x5088 6755#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 6756#define mmCGTT_SC_CLK_CTRL0 0x5089 6757#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 6758#define mmCGTT_SC_CLK_CTRL1 0x508a 6759#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 6760#define mmCGTT_SC_CLK_CTRL2 0x508b 6761#define mmCGTT_SC_CLK_CTRL2_BASE_IDX 1 6762#define mmCGTT_SQ_CLK_CTRL 0x508c 6763#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 6764#define mmCGTT_SQG_CLK_CTRL 0x508d 6765#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 6766#define mmSQ_ALU_CLK_CTRL 0x508e 6767#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 6768#define mmSQ_TEX_CLK_CTRL 0x508f 6769#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 6770#define mmSQ_LDS_CLK_CTRL 0x5090 6771#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 6772#define mmSQ_POWER_THROTTLE 0x5091 6773#define mmSQ_POWER_THROTTLE_BASE_IDX 1 6774#define mmSQ_POWER_THROTTLE2 0x5092 6775#define mmSQ_POWER_THROTTLE2_BASE_IDX 1 6776#define mmCGTT_SX_CLK_CTRL0 0x5094 6777#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 6778#define mmCGTT_SX_CLK_CTRL1 0x5095 6779#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 6780#define mmCGTT_SX_CLK_CTRL2 0x5096 6781#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 6782#define mmCGTT_SX_CLK_CTRL3 0x5097 6783#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 6784#define mmCGTT_SX_CLK_CTRL4 0x5098 6785#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 6786#define mmTD_CGTT_CTRL 0x509c 6787#define mmTD_CGTT_CTRL_BASE_IDX 1 6788#define mmTA_CGTT_CTRL 0x509d 6789#define mmTA_CGTT_CTRL_BASE_IDX 1 6790#define mmCGTT_TCPI_CLK_CTRL 0x509e 6791#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 6792#define mmCGTT_TCI_CLK_CTRL 0x509f 6793#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1 6794#define mmCGTT_GDS_CLK_CTRL 0x50a0 6795#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 6796#define mmDB_CGTT_CLK_CTRL_0 0x50a4 6797#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 6798#define mmCB_CGTT_SCLK_CTRL 0x50a8 6799#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 6800#define mmTCC_CGTT_SCLK_CTRL 0x50ac 6801#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1 6802#define mmTCA_CGTT_SCLK_CTRL 0x50ad 6803#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1 6804#define mmCGTT_CP_CLK_CTRL 0x50b0 6805#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 6806#define mmCGTT_CPF_CLK_CTRL 0x50b1 6807#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 6808#define mmCGTT_CPC_CLK_CTRL 0x50b2 6809#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 6810#define mmCGTT_RLC_CLK_CTRL 0x50b5 6811#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 6812#define mmRLC_GFX_RM_CNTL 0x50b6 6813#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 6814#define mmRMI_CGTT_SCLK_CTRL 0x50c0 6815#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 6816#define mmCGTT_TCPF_CLK_CTRL 0x50c1 6817#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 6818#define mmSE_CAC_CGTT_CLK_CTRL 0x50d0 6819#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 6820#define mmGC_CAC_CGTT_CLK_CTRL 0x50d8 6821#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 6822#define mmGRBM_CGTT_CLK_CNTL 0x50e0 6823#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 1 6824 6825 6826// addressBlock: gc_ea_pwrdec 6827// base address: 0x3c000 6828#define mmGCEA_CGTT_CLK_CTRL 0x50c4 6829#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 6830 6831 6832// addressBlock: gc_utcl2_vmsharedhvdec 6833// base address: 0x3ea00 6834#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 6835#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 6836#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 6837#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 6838#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 6839#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 6840#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 6841#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 6842#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 6843#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 6844#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 6845#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 6846#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 6847#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 6848#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 6849#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 6850#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 6851#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 6852#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 6853#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 6854#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 6855#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 6856#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 6857#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 6858#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 6859#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 6860#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 6861#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 6862#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 6863#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 6864#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 6865#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 6866#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90 6867#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 6868#define mmMC_VM_MARC_BASE_LO_0 0x5a91 6869#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1 6870#define mmMC_VM_MARC_BASE_LO_1 0x5a92 6871#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1 6872#define mmMC_VM_MARC_BASE_LO_2 0x5a93 6873#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1 6874#define mmMC_VM_MARC_BASE_LO_3 0x5a94 6875#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1 6876#define mmMC_VM_MARC_BASE_HI_0 0x5a95 6877#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1 6878#define mmMC_VM_MARC_BASE_HI_1 0x5a96 6879#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1 6880#define mmMC_VM_MARC_BASE_HI_2 0x5a97 6881#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1 6882#define mmMC_VM_MARC_BASE_HI_3 0x5a98 6883#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1 6884#define mmMC_VM_MARC_RELOC_LO_0 0x5a99 6885#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 6886#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a 6887#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 6888#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b 6889#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 6890#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c 6891#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 6892#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d 6893#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 6894#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e 6895#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 6896#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f 6897#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 6898#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0 6899#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 6900#define mmMC_VM_MARC_LEN_LO_0 0x5aa1 6901#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1 6902#define mmMC_VM_MARC_LEN_LO_1 0x5aa2 6903#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1 6904#define mmMC_VM_MARC_LEN_LO_2 0x5aa3 6905#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1 6906#define mmMC_VM_MARC_LEN_LO_3 0x5aa4 6907#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1 6908#define mmMC_VM_MARC_LEN_HI_0 0x5aa5 6909#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1 6910#define mmMC_VM_MARC_LEN_HI_1 0x5aa6 6911#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1 6912#define mmMC_VM_MARC_LEN_HI_2 0x5aa7 6913#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1 6914#define mmMC_VM_MARC_LEN_HI_3 0x5aa8 6915#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1 6916#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9 6917#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 6918#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa 6919#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 6920#define mmVM_PCIE_ATS_CNTL 0x5aab 6921#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1 6922#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac 6923#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 6924#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad 6925#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 6926#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae 6927#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 6928#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf 6929#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 6930#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0 6931#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 6932#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1 6933#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 6934#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2 6935#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 6936#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3 6937#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 6938#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4 6939#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 6940#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5 6941#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 6942#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6 6943#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 6944#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7 6945#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 6946#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8 6947#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 6948#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9 6949#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 6950#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba 6951#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 6952#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb 6953#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 6954#define mmUTCL2_CGTT_CLK_CTRL 0x5abc 6955#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 6956#define mmMC_SHARED_ACTIVE_FCN_ID 0x5abd 6957#define mmMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 6958#define mmMC_VM_XGMI_GPUIOV_ENABLE 0x5abe 6959#define mmMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 6960 6961 6962// addressBlock: gc_hypdec 6963// base address: 0x3e000 6964#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 6965#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 6966#define mmCP_PFP_UCODE_ADDR 0x5814 6967#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 6968#define mmCP_HYP_PFP_UCODE_DATA 0x5815 6969#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 6970#define mmCP_PFP_UCODE_DATA 0x5815 6971#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 6972#define mmCP_HYP_ME_UCODE_ADDR 0x5816 6973#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 6974#define mmCP_ME_RAM_RADDR 0x5816 6975#define mmCP_ME_RAM_RADDR_BASE_IDX 1 6976#define mmCP_ME_RAM_WADDR 0x5816 6977#define mmCP_ME_RAM_WADDR_BASE_IDX 1 6978#define mmCP_HYP_ME_UCODE_DATA 0x5817 6979#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 6980#define mmCP_ME_RAM_DATA 0x5817 6981#define mmCP_ME_RAM_DATA_BASE_IDX 1 6982#define mmCP_CE_UCODE_ADDR 0x5818 6983#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 6984#define mmCP_HYP_CE_UCODE_ADDR 0x5818 6985#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 6986#define mmCP_CE_UCODE_DATA 0x5819 6987#define mmCP_CE_UCODE_DATA_BASE_IDX 1 6988#define mmCP_HYP_CE_UCODE_DATA 0x5819 6989#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 6990#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a 6991#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 6992#define mmCP_MEC_ME1_UCODE_ADDR 0x581a 6993#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 6994#define mmCP_HYP_MEC1_UCODE_DATA 0x581b 6995#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 6996#define mmCP_MEC_ME1_UCODE_DATA 0x581b 6997#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 6998#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c 6999#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 7000#define mmCP_MEC_ME2_UCODE_ADDR 0x581c 7001#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 7002#define mmCP_HYP_MEC2_UCODE_DATA 0x581d 7003#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 7004#define mmCP_MEC_ME2_UCODE_DATA 0x581d 7005#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 7006#define mmCP_HYP_PFP_UCODE_CHKSUM 0x581e 7007#define mmCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 7008#define mmCP_HYP_CE_UCODE_CHKSUM 0x581f 7009#define mmCP_HYP_CE_UCODE_CHKSUM_BASE_IDX 1 7010#define mmCP_HYP_ME_UCODE_CHKSUM 0x5820 7011#define mmCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 7012#define mmCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 7013#define mmCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 7014#define mmCP_HYP_MEC_ME2_UCODE_CHKSUM 0x5822 7015#define mmCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX 1 7016#define mmRLC_GPM_UCODE_ADDR 0x583c 7017#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 7018#define mmRLC_GPM_UCODE_DATA 0x583d 7019#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 7020#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 7021#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 7022#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 7023#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 7024#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 7025#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 7026#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 7027#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 7028#define mmGRBM_CAM_INDEX 0x5a04 7029#define mmGRBM_CAM_INDEX_BASE_IDX 1 7030#define mmGRBM_HYP_CAM_INDEX 0x5a04 7031#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 7032#define mmGRBM_CAM_DATA 0x5a05 7033#define mmGRBM_CAM_DATA_BASE_IDX 1 7034#define mmGRBM_HYP_CAM_DATA 0x5a05 7035#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1 7036#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 7037#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 7038#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 7039#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 7040#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 7041#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 7042#define mmRLC_RLCV_TIMER_INT_0 0x5b25 7043#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 7044#define mmRLC_RLCV_TIMER_CTRL 0x5b26 7045#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 7046#define mmRLC_RLCV_TIMER_STAT 0x5b27 7047#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 7048#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 7049#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 7050#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 7051#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 7052#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 7053#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 7054#define mmRLC_GPU_IOV_VF_MASK 0x5b2d 7055#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 7056#define mmRLC_HYP_SEMAPHORE_0 0x5b2e 7057#define mmRLC_HYP_SEMAPHORE_0_BASE_IDX 1 7058#define mmRLC_HYP_SEMAPHORE_1 0x5b2f 7059#define mmRLC_HYP_SEMAPHORE_1_BASE_IDX 1 7060#define mmRLC_CLK_CNTL 0x5b31 7061#define mmRLC_CLK_CNTL_BASE_IDX 1 7062#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 7063#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 7064#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 7065#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 7066#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 7067#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 7068#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 7069#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 7070#define mmRLC_GPU_IOV_SCH_0 0x5b38 7071#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 7072#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 7073#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 7074#define mmRLC_GPU_IOV_SCH_3 0x5b3a 7075#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 7076#define mmRLC_GPU_IOV_SCH_1 0x5b3b 7077#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 7078#define mmRLC_GPU_IOV_SCH_2 0x5b3c 7079#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 7080#define mmRLC_GPU_IOV_INT_STAT 0x5b3f 7081#define mmRLC_GPU_IOV_INT_STAT_BASE_IDX 1 7082#define mmRLC_RLCV_TIMER_INT_1 0x5b40 7083#define mmRLC_RLCV_TIMER_INT_1_BASE_IDX 1 7084#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42 7085#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 7086#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43 7087#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 7088#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 7089#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 7090#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45 7091#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 7092#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 7093#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 7094#define mmRLC_GPU_IOV_F32_RESET 0x5b47 7095#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 7096#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48 7097#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 7098#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49 7099#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 7100#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a 7101#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 7102#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c 7103#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 7104#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 7105#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 7106#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e 7107#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 7108#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f 7109#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 7110#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 7111#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 7112#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 7113#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 7114#define mmRLC_HYP_SEMAPHORE_2 0x5b52 7115#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 7116#define mmRLC_HYP_SEMAPHORE_3 0x5b53 7117#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 7118 7119 7120// addressBlock: gccacind 7121// base address: 0x0 7122#define ixGC_CAC_CNTL 0x0000 7123#define ixGC_CAC_OVR_SEL 0x0001 7124#define ixGC_CAC_OVR_VAL 0x0002 7125#define ixGC_CAC_WEIGHT_BCI_0 0x0003 7126#define ixGC_CAC_WEIGHT_CB_0 0x0004 7127#define ixGC_CAC_WEIGHT_CB_1 0x0005 7128#define ixGC_CAC_WEIGHT_CP_0 0x0008 7129#define ixGC_CAC_WEIGHT_CP_1 0x0009 7130#define ixGC_CAC_WEIGHT_DB_0 0x000a 7131#define ixGC_CAC_WEIGHT_DB_1 0x000b 7132#define ixGC_CAC_WEIGHT_GDS_0 0x000e 7133#define ixGC_CAC_WEIGHT_GDS_1 0x000f 7134#define ixGC_CAC_WEIGHT_IA_0 0x0010 7135#define ixGC_CAC_WEIGHT_LDS_0 0x0011 7136#define ixGC_CAC_WEIGHT_LDS_1 0x0012 7137#define ixGC_CAC_WEIGHT_PA_0 0x0013 7138#define ixGC_CAC_WEIGHT_PC_0 0x0014 7139#define ixGC_CAC_WEIGHT_SC_0 0x0015 7140#define ixGC_CAC_WEIGHT_SPI_0 0x0016 7141#define ixGC_CAC_WEIGHT_SPI_1 0x0017 7142#define ixGC_CAC_WEIGHT_SPI_2 0x0018 7143#define ixGC_CAC_WEIGHT_SQ_0 0x001a 7144#define ixGC_CAC_WEIGHT_SQ_1 0x001b 7145#define ixGC_CAC_WEIGHT_SQ_2 0x001c 7146#define ixGC_CAC_WEIGHT_SQ_3 0x001d 7147#define ixGC_CAC_WEIGHT_SQ_4 0x001e 7148#define ixGC_CAC_WEIGHT_SX_0 0x001f 7149#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 7150#define ixGC_CAC_WEIGHT_TA_0 0x0021 7151#define ixGC_CAC_WEIGHT_TCC_0 0x0022 7152#define ixGC_CAC_WEIGHT_TCC_1 0x0023 7153#define ixGC_CAC_WEIGHT_TCC_2 0x0024 7154#define ixGC_CAC_WEIGHT_TCP_0 0x0025 7155#define ixGC_CAC_WEIGHT_TCP_1 0x0026 7156#define ixGC_CAC_WEIGHT_TCP_2 0x0027 7157#define ixGC_CAC_WEIGHT_TD_0 0x0028 7158#define ixGC_CAC_WEIGHT_TD_1 0x0029 7159#define ixGC_CAC_WEIGHT_TD_2 0x002a 7160#define ixGC_CAC_WEIGHT_VGT_0 0x002b 7161#define ixGC_CAC_WEIGHT_VGT_1 0x002c 7162#define ixGC_CAC_WEIGHT_WD_0 0x002d 7163#define ixGC_CAC_WEIGHT_CU_0 0x0032 7164#define ixGC_CAC_ACC_BCI0 0x0042 7165#define ixGC_CAC_ACC_CB0 0x0043 7166#define ixGC_CAC_ACC_CB1 0x0044 7167#define ixGC_CAC_ACC_CB2 0x0045 7168#define ixGC_CAC_ACC_CB3 0x0046 7169#define ixGC_CAC_ACC_CP0 0x004b 7170#define ixGC_CAC_ACC_CP1 0x004c 7171#define ixGC_CAC_ACC_CP2 0x004d 7172#define ixGC_CAC_ACC_DB0 0x004e 7173#define ixGC_CAC_ACC_DB1 0x004f 7174#define ixGC_CAC_ACC_DB2 0x0050 7175#define ixGC_CAC_ACC_DB3 0x0051 7176#define ixGC_CAC_ACC_GDS0 0x0056 7177#define ixGC_CAC_ACC_GDS1 0x0057 7178#define ixGC_CAC_ACC_GDS2 0x0058 7179#define ixGC_CAC_ACC_GDS3 0x0059 7180#define ixGC_CAC_ACC_IA0 0x005a 7181#define ixGC_CAC_ACC_LDS0 0x005b 7182#define ixGC_CAC_ACC_LDS1 0x005c 7183#define ixGC_CAC_ACC_LDS2 0x005d 7184#define ixGC_CAC_ACC_LDS3 0x005e 7185#define ixGC_CAC_ACC_PA0 0x005f 7186#define ixGC_CAC_ACC_PA1 0x0060 7187#define ixGC_CAC_ACC_PC0 0x0061 7188#define ixGC_CAC_ACC_SC0 0x0062 7189#define ixGC_CAC_ACC_SPI0 0x0063 7190#define ixGC_CAC_ACC_SPI1 0x0064 7191#define ixGC_CAC_ACC_SPI2 0x0065 7192#define ixGC_CAC_ACC_SPI3 0x0066 7193#define ixGC_CAC_ACC_SPI4 0x0067 7194#define ixGC_CAC_ACC_SPI5 0x0068 7195#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f 7196#define ixGC_CAC_ACC_EA0 0x0070 7197#define ixGC_CAC_ACC_EA1 0x0071 7198#define ixGC_CAC_ACC_EA2 0x0072 7199#define ixGC_CAC_ACC_EA3 0x0073 7200#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 7201#define ixGC_CAC_OVRD_EA 0x0075 7202#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 7203#define ixGC_CAC_WEIGHT_EA_0 0x0077 7204#define ixGC_CAC_WEIGHT_EA_1 0x0078 7205#define ixGC_CAC_WEIGHT_RMI_0 0x0079 7206#define ixGC_CAC_ACC_RMI0 0x007a 7207#define ixGC_CAC_OVRD_RMI 0x007b 7208#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c 7209#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d 7210#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e 7211#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f 7212#define ixGC_CAC_ACC_EA4 0x0080 7213#define ixGC_CAC_ACC_EA5 0x0081 7214#define ixGC_CAC_WEIGHT_EA_2 0x0082 7215#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 7216#define ixGC_CAC_ACC_SQ0_UPPER 0x008a 7217#define ixGC_CAC_ACC_SQ1_LOWER 0x008b 7218#define ixGC_CAC_ACC_SQ1_UPPER 0x008c 7219#define ixGC_CAC_ACC_SQ2_LOWER 0x008d 7220#define ixGC_CAC_ACC_SQ2_UPPER 0x008e 7221#define ixGC_CAC_ACC_SQ3_LOWER 0x008f 7222#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 7223#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 7224#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 7225#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 7226#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 7227#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 7228#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 7229#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 7230#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 7231#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 7232#define ixGC_CAC_ACC_SQ8_UPPER 0x009a 7233#define ixGC_CAC_ACC_SX0 0x009b 7234#define ixGC_CAC_ACC_SXRB0 0x009c 7235#define ixGC_CAC_ACC_SXRB1 0x009d 7236#define ixGC_CAC_ACC_TA0 0x009e 7237#define ixGC_CAC_ACC_TCC0 0x009f 7238#define ixGC_CAC_ACC_TCC1 0x00a0 7239#define ixGC_CAC_ACC_TCC2 0x00a1 7240#define ixGC_CAC_ACC_TCC3 0x00a2 7241#define ixGC_CAC_ACC_TCC4 0x00a3 7242#define ixGC_CAC_ACC_TCP0 0x00a4 7243#define ixGC_CAC_ACC_TCP1 0x00a5 7244#define ixGC_CAC_ACC_TCP2 0x00a6 7245#define ixGC_CAC_ACC_TCP3 0x00a7 7246#define ixGC_CAC_ACC_TCP4 0x00a8 7247#define ixGC_CAC_ACC_TD0 0x00a9 7248#define ixGC_CAC_ACC_TD1 0x00aa 7249#define ixGC_CAC_ACC_TD2 0x00ab 7250#define ixGC_CAC_ACC_TD3 0x00ac 7251#define ixGC_CAC_ACC_TD4 0x00ad 7252#define ixGC_CAC_ACC_TD5 0x00ae 7253#define ixGC_CAC_ACC_VGT0 0x00af 7254#define ixGC_CAC_ACC_VGT1 0x00b0 7255#define ixGC_CAC_ACC_VGT2 0x00b1 7256#define ixGC_CAC_ACC_WD0 0x00b2 7257#define ixGC_CAC_ACC_CU0 0x00ba 7258#define ixGC_CAC_ACC_CU1 0x00bb 7259#define ixGC_CAC_ACC_CU2 0x00bc 7260#define ixGC_CAC_ACC_CU3 0x00bd 7261#define ixGC_CAC_ACC_CU4 0x00be 7262#define ixGC_CAC_OVRD_BCI 0x00da 7263#define ixGC_CAC_OVRD_CB 0x00db 7264#define ixGC_CAC_OVRD_CP 0x00dd 7265#define ixGC_CAC_OVRD_DB 0x00de 7266#define ixGC_CAC_OVRD_GDS 0x00e0 7267#define ixGC_CAC_OVRD_IA 0x00e1 7268#define ixGC_CAC_OVRD_LDS 0x00e2 7269#define ixGC_CAC_OVRD_PA 0x00e3 7270#define ixGC_CAC_OVRD_PC 0x00e4 7271#define ixGC_CAC_OVRD_SC 0x00e5 7272#define ixGC_CAC_OVRD_SPI 0x00e6 7273#define ixGC_CAC_OVRD_CU 0x00e7 7274#define ixGC_CAC_OVRD_SQ 0x00e8 7275#define ixGC_CAC_OVRD_SX 0x00e9 7276#define ixGC_CAC_OVRD_SXRB 0x00ea 7277#define ixGC_CAC_OVRD_TA 0x00eb 7278#define ixGC_CAC_OVRD_TCC 0x00ec 7279#define ixGC_CAC_OVRD_TCP 0x00ed 7280#define ixGC_CAC_OVRD_TD 0x00ee 7281#define ixGC_CAC_OVRD_VGT 0x00ef 7282#define ixGC_CAC_OVRD_WD 0x00f0 7283#define ixGC_CAC_ACC_BCI1 0x00ff 7284#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 7285#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 7286#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 7287#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 7288#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 7289#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 7290#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 7291#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 7292#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 7293#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 7294#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a 7295#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b 7296#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c 7297#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d 7298#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e 7299#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f 7300#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 7301#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 7302#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 7303#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 7304#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 7305#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 7306#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 7307#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 7308#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 7309#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 7310#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a 7311#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b 7312#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c 7313#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d 7314#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e 7315#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f 7316#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 7317#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 7318#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 7319#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 7320#define ixPCC_STALL_PATTERN_1_2 0x0134 7321#define ixPCC_STALL_PATTERN_3_4 0x0135 7322#define ixPCC_STALL_PATTERN_5_6 0x0136 7323#define ixPCC_STALL_PATTERN_7 0x0137 7324#define ixPCC_THROT_REINCR_FIRST_PATN_1_8 0x0138 7325#define ixPCC_THROT_REINCR_FIRST_PATN_9_16 0x0139 7326#define ixPCC_THROT_REINCR_FIRST_PATN_17_20 0x0140 7327#define ixPCC_THROT_DECR_FIRST_PATN_1_4 0x0141 7328#define ixPCC_THROT_DECR_FIRST_PATN_5_7 0x0142 7329 7330 7331// addressBlock: secacind 7332// base address: 0x0 7333#define ixSE_CAC_CNTL 0x0000 7334#define ixSE_CAC_OVR_SEL 0x0001 7335#define ixSE_CAC_OVR_VAL 0x0002 7336 7337 7338// addressBlock: sqind 7339// base address: 0x0 7340#define ixSQ_WAVE_MODE 0x0011 7341#define ixSQ_WAVE_STATUS 0x0012 7342#define ixSQ_WAVE_TRAPSTS 0x0013 7343#define ixSQ_WAVE_HW_ID 0x0014 7344#define ixSQ_WAVE_GPR_ALLOC 0x0015 7345#define ixSQ_WAVE_LDS_ALLOC 0x0016 7346#define ixSQ_WAVE_IB_STS 0x0017 7347#define ixSQ_WAVE_PC_LO 0x0018 7348#define ixSQ_WAVE_PC_HI 0x0019 7349#define ixSQ_WAVE_INST_DW0 0x001a 7350#define ixSQ_WAVE_INST_DW1 0x001b 7351#define ixSQ_WAVE_IB_DBG0 0x001c 7352#define ixSQ_WAVE_IB_DBG1 0x001d 7353#define ixSQ_WAVE_FLUSH_IB 0x001e 7354#define ixSQ_WAVE_TTMP0 0x026c 7355#define ixSQ_WAVE_TTMP1 0x026d 7356#define ixSQ_WAVE_TTMP2 0x026e 7357#define ixSQ_WAVE_TTMP3 0x026f 7358#define ixSQ_WAVE_TTMP4 0x0270 7359#define ixSQ_WAVE_TTMP5 0x0271 7360#define ixSQ_WAVE_TTMP6 0x0272 7361#define ixSQ_WAVE_TTMP7 0x0273 7362#define ixSQ_WAVE_TTMP8 0x0274 7363#define ixSQ_WAVE_TTMP9 0x0275 7364#define ixSQ_WAVE_TTMP10 0x0276 7365#define ixSQ_WAVE_TTMP11 0x0277 7366#define ixSQ_WAVE_TTMP12 0x0278 7367#define ixSQ_WAVE_TTMP13 0x0279 7368#define ixSQ_WAVE_TTMP14 0x027a 7369#define ixSQ_WAVE_TTMP15 0x027b 7370#define ixSQ_WAVE_M0 0x027c 7371#define ixSQ_WAVE_EXEC_LO 0x027e 7372#define ixSQ_WAVE_EXEC_HI 0x027f 7373#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 7374#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 7375#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 7376#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 7377#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 7378#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 7379#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 7380#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 7381 7382 7383// addressBlock: didtind 7384// base address: 0x0 7385#define ixDIDT_SQ_CTRL0 0x0000 7386#define ixDIDT_SQ_CTRL2 0x0002 7387#define ixDIDT_SQ_STALL_CTRL 0x0004 7388#define ixDIDT_SQ_TUNING_CTRL 0x0005 7389#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 7390#define ixDIDT_SQ_CTRL3 0x0007 7391#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 7392#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 7393#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a 7394#define ixDIDT_SQ_STALL_PATTERN_7 0x000b 7395#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c 7396#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d 7397#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e 7398#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f 7399#define ixDIDT_SQ_WEIGHT0_3 0x0010 7400#define ixDIDT_SQ_WEIGHT4_7 0x0011 7401#define ixDIDT_SQ_WEIGHT8_11 0x0012 7402#define ixDIDT_SQ_EDC_CTRL 0x0013 7403#define ixDIDT_SQ_THROTTLE_CTRL 0x0014 7404#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 7405#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 7406#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 7407#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 7408#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a 7409#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b 7410#define ixDIDT_DB_CTRL0 0x0020 7411#define ixDIDT_DB_CTRL2 0x0022 7412#define ixDIDT_DB_STALL_CTRL 0x0024 7413#define ixDIDT_DB_TUNING_CTRL 0x0025 7414#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 7415#define ixDIDT_DB_CTRL3 0x0027 7416#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 7417#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 7418#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a 7419#define ixDIDT_DB_STALL_PATTERN_7 0x002b 7420#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c 7421#define ixDIDT_DB_THROTTLE_CNTL0 0x002d 7422#define ixDIDT_DB_THROTTLE_CNTL1 0x002e 7423#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f 7424#define ixDIDT_DB_WEIGHT0_3 0x0030 7425#define ixDIDT_DB_WEIGHT4_7 0x0031 7426#define ixDIDT_DB_WEIGHT8_11 0x0032 7427#define ixDIDT_DB_EDC_CTRL 0x0033 7428#define ixDIDT_DB_THROTTLE_CTRL 0x0034 7429#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 7430#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 7431#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 7432#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 7433#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a 7434#define ixDIDT_TD_CTRL0 0x0040 7435#define ixDIDT_TD_CTRL2 0x0042 7436#define ixDIDT_TD_STALL_CTRL 0x0044 7437#define ixDIDT_TD_TUNING_CTRL 0x0045 7438#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 7439#define ixDIDT_TD_CTRL3 0x0047 7440#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 7441#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 7442#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a 7443#define ixDIDT_TD_STALL_PATTERN_7 0x004b 7444#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c 7445#define ixDIDT_TD_THROTTLE_CNTL0 0x004d 7446#define ixDIDT_TD_THROTTLE_CNTL1 0x004e 7447#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f 7448#define ixDIDT_TD_WEIGHT0_3 0x0050 7449#define ixDIDT_TD_WEIGHT4_7 0x0051 7450#define ixDIDT_TD_WEIGHT8_11 0x0052 7451#define ixDIDT_TD_EDC_CTRL 0x0053 7452#define ixDIDT_TD_THROTTLE_CTRL 0x0054 7453#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 7454#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 7455#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 7456#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 7457#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a 7458#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b 7459#define ixDIDT_TCP_CTRL0 0x0060 7460#define ixDIDT_TCP_CTRL2 0x0062 7461#define ixDIDT_TCP_STALL_CTRL 0x0064 7462#define ixDIDT_TCP_TUNING_CTRL 0x0065 7463#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 7464#define ixDIDT_TCP_CTRL3 0x0067 7465#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 7466#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 7467#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a 7468#define ixDIDT_TCP_STALL_PATTERN_7 0x006b 7469#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x006c 7470#define ixDIDT_TCP_THROTTLE_CNTL0 0x006d 7471#define ixDIDT_TCP_THROTTLE_CNTL1 0x006e 7472#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0x006f 7473#define ixDIDT_TCP_WEIGHT0_3 0x0070 7474#define ixDIDT_TCP_WEIGHT4_7 0x0071 7475#define ixDIDT_TCP_WEIGHT8_11 0x0072 7476#define ixDIDT_TCP_EDC_CTRL 0x0073 7477#define ixDIDT_TCP_THROTTLE_CTRL 0x0074 7478#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 7479#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 7480#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 7481#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 7482#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a 7483#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b 7484#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 7485#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 7486#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 7487#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 7488#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 7489#define ixDIDT_SQ_CTRL1 0x00b0 7490#define ixDIDT_SQ_EDC_THRESHOLD 0x00b1 7491#define ixDIDT_DB_CTRL1 0x00b2 7492#define ixDIDT_DB_EDC_THRESHOLD 0x00b3 7493#define ixDIDT_TD_CTRL1 0x00b4 7494#define ixDIDT_TD_EDC_THRESHOLD 0x00b5 7495#define ixDIDT_TCP_CTRL1 0x00b6 7496#define ixDIDT_TCP_EDC_THRESHOLD 0x00b7 7497 7498 7499#endif 7500