Searched refs:mmATC_L2_CACHE_DATA0 (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_d.h547 #define mmATC_L2_CACHE_DATA0 0xcd9 macro
H A Dgmc_8_1_d.h545 #define mmATC_L2_CACHE_DATA0 0xcd9 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_offset.h1244 #define mmATC_L2_CACHE_DATA0 0x0644 macro
H A Dmmhub_9_1_offset.h1276 #define mmATC_L2_CACHE_DATA0 0x0644 macro
H A Dmmhub_9_3_0_offset.h1260 #define mmATC_L2_CACHE_DATA0 0x0644 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1133 #define mmATC_L2_CACHE_DATA0 0x0804 macro
H A Dgc_9_1_offset.h1166 #define mmATC_L2_CACHE_DATA0 0x0804 macro
H A Dgc_9_2_1_offset.h1104 #define mmATC_L2_CACHE_DATA0 0x0804 macro

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