Searched refs:intr_mask (Results 1 - 25 of 37) sorted by relevance

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/netbsd-current/sys/arch/arm/s3c2xx0/
H A Ds3c2800_intr.h51 #define get_pending_softint() (softint_pending & intr_mask)
56 (*s3c2xx0_intr_mask_reg = intr_mask & global_intr_mask)
H A Ds3c24x0_intr.h40 /* no room for softinterrupts in intr_mask. */
50 (*s3c2xx0_intr_mask_reg = ~(intr_mask & global_intr_mask))
H A Ds3c2xx0_intr.h88 extern volatile int intr_mask;
120 intr_mask = s3c2xx0_imask[curcpl()];
H A Ds3c2800_intr.c60 volatile int intr_mask; /* XXX: does this need to be volatile? */ variable
/netbsd-current/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mc/
H A Dnouveau_nvkm_subdev_mc_gk20a.c37 .intr_mask = gf100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_gp10b.c45 .intr_mask = gp100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_gk104.c61 .intr_mask = gf100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_tu102.c50 .intr_mask = gp100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_gt215.c73 .intr_mask = gt215_mc_intr_mask,
H A Dpriv.h29 void (*intr_mask)(struct nvkm_mc *, u32 mask, u32 stat); member in struct:nvkm_mc_func
H A Dnouveau_nvkm_subdev_mc_gp100.c115 .intr_mask = gp100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_gf100.c113 .intr_mask = gf100_mc_intr_mask,
H A Dnouveau_nvkm_subdev_mc_base.c47 if (likely(mc) && mc->func->intr_mask) {
53 mc->func->intr_mask(mc, mask, en ? mask : 0);
/netbsd-current/sys/arch/arm/xscale/
H A Dpxa2x0_intr.h59 extern volatile int intr_mask;
71 intr_mask = pxa2x0_imask[new];
72 write_icu(SAIPIC_MR, intr_mask);
H A Dpxa2x0_intr.c96 volatile int intr_mask; variable
300 intr_mask = pxa2x0_imask[curcpu()->ci_cpl];
/netbsd-current/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/gpio/
H A Dpriv.h21 void (*intr_mask)(struct nvkm_gpio *, u32, u32, u32); member in struct:nvkm_gpio_func
H A Dnouveau_nvkm_subdev_gpio_gf119.c81 .intr_mask = g94_gpio_intr_mask,
H A Dnouveau_nvkm_subdev_gpio_gk104.c69 .intr_mask = gk104_gpio_intr_mask,
H A Dnouveau_nvkm_subdev_gpio_g94.c69 .intr_mask = g94_gpio_intr_mask,
H A Dnouveau_nvkm_subdev_gpio_base.c121 gpio->func->intr_mask(gpio, type, 1 << index, 0);
128 gpio->func->intr_mask(gpio, type, 1 << index, 1 << index);
175 gpio->func->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0);
H A Dnouveau_nvkm_subdev_gpio_nv10.c114 .intr_mask = nv10_gpio_intr_mask,
/netbsd-current/sys/dev/isa/
H A Di82365_isasubr.c185 device_xname(sc->dev), h->chip, sc->intr_mask[h->chip]);
210 if ((sc->intr_mask[h->chip] & (1 << i)) == 0)
258 sc->intr_mask[h->chip] = mask;
260 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none");
290 sc->intr_mask[h->chip] =
298 chipmask &= sc->intr_mask[h->chip];
306 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) {
473 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq))
/netbsd-current/sys/external/bsd/dwc2/dist/
H A Ddwc2_hcdqueue.c666 u32 intr_mask; local
704 intr_mask = DWC2_READ_4(hsotg, GINTMSK);
705 intr_mask |= GINTSTS_SOF;
706 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
722 u32 intr_mask; local
744 intr_mask = DWC2_READ_4(hsotg, GINTMSK);
745 intr_mask &= ~GINTSTS_SOF;
746 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
/netbsd-current/sys/arch/x86/include/
H A Dintr.h106 * is because intr_mask() can be called from an interrupt handler.
219 void intr_mask(struct intrhand *);
/netbsd-current/sys/dev/ic/
H A Di82365var.h158 int intr_mask[PCIC_NSLOTS / 2]; /* probed intterupts if possible */ member in struct:pcic_softc

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