1/*	$NetBSD: nouveau_nvkm_subdev_mc_gf100.c,v 1.3 2021/12/18 23:45:40 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_mc_gf100.c,v 1.3 2021/12/18 23:45:40 riastradh Exp $");
28
29#include "priv.h"
30
31static const struct nvkm_mc_map
32gf100_mc_reset[] = {
33	{ 0x00020000, NVKM_ENGINE_MSPDEC },
34	{ 0x00008000, NVKM_ENGINE_MSVLD },
35	{ 0x00002000, NVKM_SUBDEV_PMU, true },
36	{ 0x00001000, NVKM_ENGINE_GR },
37	{ 0x00000100, NVKM_ENGINE_FIFO },
38	{ 0x00000080, NVKM_ENGINE_CE1 },
39	{ 0x00000040, NVKM_ENGINE_CE0 },
40	{ 0x00000002, NVKM_ENGINE_MSPPP },
41	{}
42};
43
44static const struct nvkm_mc_map
45gf100_mc_intr[] = {
46	{ 0x04000000, NVKM_ENGINE_DISP },
47	{ 0x00020000, NVKM_ENGINE_MSPDEC },
48	{ 0x00008000, NVKM_ENGINE_MSVLD },
49	{ 0x00001000, NVKM_ENGINE_GR },
50	{ 0x00000100, NVKM_ENGINE_FIFO },
51	{ 0x00000040, NVKM_ENGINE_CE1 },
52	{ 0x00000020, NVKM_ENGINE_CE0 },
53	{ 0x00000001, NVKM_ENGINE_MSPPP },
54	{ 0x40000000, NVKM_SUBDEV_IBUS },
55	{ 0x10000000, NVKM_SUBDEV_BUS },
56	{ 0x08000000, NVKM_SUBDEV_FB },
57	{ 0x02000000, NVKM_SUBDEV_LTC },
58	{ 0x01000000, NVKM_SUBDEV_PMU },
59	{ 0x00200000, NVKM_SUBDEV_GPIO },
60	{ 0x00200000, NVKM_SUBDEV_I2C },
61	{ 0x00100000, NVKM_SUBDEV_TIMER },
62	{ 0x00040000, NVKM_SUBDEV_THERM },
63	{ 0x00002000, NVKM_SUBDEV_FB },
64	{},
65};
66
67void
68gf100_mc_intr_unarm(struct nvkm_mc *mc)
69{
70	struct nvkm_device *device = mc->subdev.device;
71	nvkm_wr32(device, 0x000140, 0x00000000);
72	nvkm_wr32(device, 0x000144, 0x00000000);
73	nvkm_rd32(device, 0x000140);
74}
75
76void
77gf100_mc_intr_rearm(struct nvkm_mc *mc)
78{
79	struct nvkm_device *device = mc->subdev.device;
80	nvkm_wr32(device, 0x000140, 0x00000001);
81	nvkm_wr32(device, 0x000144, 0x00000001);
82}
83
84u32
85gf100_mc_intr_stat(struct nvkm_mc *mc)
86{
87	struct nvkm_device *device = mc->subdev.device;
88	u32 intr0 = nvkm_rd32(device, 0x000100);
89	u32 intr1 = nvkm_rd32(device, 0x000104);
90	return intr0 | intr1;
91}
92
93void
94gf100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat)
95{
96	struct nvkm_device *device = mc->subdev.device;
97	nvkm_mask(device, 0x000640, mask, stat);
98	nvkm_mask(device, 0x000644, mask, stat);
99}
100
101void
102gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
103{
104	nvkm_wr32(mc->subdev.device, 0x000260, data);
105}
106
107static const struct nvkm_mc_func
108gf100_mc = {
109	.init = nv50_mc_init,
110	.intr = gf100_mc_intr,
111	.intr_unarm = gf100_mc_intr_unarm,
112	.intr_rearm = gf100_mc_intr_rearm,
113	.intr_mask = gf100_mc_intr_mask,
114	.intr_stat = gf100_mc_intr_stat,
115	.reset = gf100_mc_reset,
116	.unk260 = gf100_mc_unk260,
117};
118
119int
120gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
121{
122	return nvkm_mc_new_(&gf100_mc, device, index, pmc);
123}
124